牛客verilog 自动贩卖机1

module    sale1
(
    input        wire        clk,
    input        wire        rst_n,
    input        wire [1:0]    d,
    
    output        reg            q,
    output        reg     [1:0]    s        
);

parameter    IDLE = 2'b00,
            S1     = 2'b01,
            S2     = 2'b10;

reg        [1:0]    state;
reg        [1:0]    next_state;

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        state <= IDLE;
    else
        state <= next_state;
        
always@(*)
    begin
        if(!rst_n)
            next_state <= IDLE;
        else
            begin
                case(state)
                    IDLE:
                        if(d == 2'b00)
                            next_state <= IDLE;
                        else if(d == 2'b01)
                            next_state <= S1;
                        else if(d == 2'b10)
                            next_state <= S2;
                        else
                            next_state <= IDLE;
                    S1  :
                        if(d == 2'b00)
                            next_state <= S1;
                        else if(d == 2'b01)
                            next_state <= S2;
                        else
                            next_state <= IDLE;
                    S2    :
                        if(d == 2'b00)
                            next_state <= S2;
                        else
                            next_state;    
                    default: next_state <= IDLE;
                endcase
            end
    end

//描述输出状态
always@(posedge clk or negedge rst_n)
    if(!rst_n)
        begin
            q <= 1'b0;
            s <= 2'b0;
        end
    else
        case(next_state)
            IDLE :
                begin
                    q <= (d == 2'b11)? 1'b1 : 1'b0;
                    s <= (d == 2'b11)? 2'b01: 2'b00;
                end
            S1     :
                begin
                    q <= (d==2'b10 || d==2'b11) ? 1'b1 : 1'b0;
                    s <= (d==2'b11)? 2'b10: 2'b00;
                end
            S2     :
                begin
                    q <= (d==2'b01 || d==2'b10 || d==2'b11) ? 1'b1 :1'b0;
                    s <= (d==2'b01) ? 2'b00 :1'b0;
                    s <= (d==2'b10) ? 2'b01 :1'b0;
                    s <= (d==2'b11) ? 2'b11 :1'b0;
                end
            default:
                begin
                    q <= 1'b0;
                    s <= 2'b0;
                end
        endcase

endmodule