[vivado]在使用1G/2.5G Ethernet PCS/PMA or SGMII(16.2) IP核心配置1G SGMII模式gig_ethernet_pcs_pma_IP时需注意的内容

关注

原创最新推荐文章于 2026-10-04 09:40:56 发布 1k 阅读 AI 写同款· GEO 优化 ›

Xilinx的IP核gig_ethernet_pcs_pma例化案例 Xilinx的IP核gig_ethernet_pcs_pma例化案例1G/2.5G Ethernet PCS/PMA or SGMII v16.1IP核例化计数开头的55,判断1000M或者100M以太网数据异步缓存FIFO总结 1G/2.5G Ethernet PCS/PMA or SGMII v16.1 废话不BB，直接用。手册看完，一礼拜没理解透。理解出现偏差。最后实验出真知。 IP核例化 gig_ethernet_pcs_pma_0 gig_ethernet_pcs_pma_0 ( .gtref 阅读详情

在使用此ETH IP时需注意接收端为gmii时需要进行时序约束约束举例如下

###############################################################################
# Timing Constraints
###############################################################################
create_clock -period 10.000 -name sys_clk [get_ports sys_clk_p]
create_clock -period 8.000 -name sgmii_ref0_clk_p -waveform {0.000 4.000} [get_ports sgmii_ref0_clk_p]
set_input_delay -clock [get_clocks -of_objects [get_pins axi_pcie_0_i/pcie_slave_i/axi_pcie_0/inst/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT3]] -max 2.000 [get_pins {eth_gmac_top_u/eth_redu_phy_u/gig_ethernet_pcs_pma_0_support_u/phy_gmii_rxd[*]}]
set_input_delay -clock [get_clocks -of_objects [get_pins axi_pcie_0_i/pcie_slave_i/axi_pcie_0/inst/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT3]] -min -1.000 [get_pins {eth_gmac_top_u/eth_redu_phy_u/gig_ethernet_pcs_pma_0_support_u/phy_gmii_rxd[*]}]
set_input_delay -clock [get_clocks -of_objects [get_pins axi_pcie_0_i/pcie_slave_i/axi_pcie_0/inst/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT3]] -max 2.000 [get_pins {eth_gmac_top_u/eth_redu_phy_u/gig_ethernet_pcs_pma_0_support_u/phy_gmii_rx_er[*]}]
set_input_delay -clock [get_clocks -of_objects [get_pins axi_pcie_0_i/pcie_slave_i/axi_pcie_0/inst/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT3]] -min -1.000 [get_pins {eth_gmac_top_u/eth_redu_phy_u/gig_ethernet_pcs_pma_0_support_u/phy_gmii_rx_er[*]}]
set_input_delay -clock [get_clocks -of_objects [get_pins axi_pcie_0_i/pcie_slave_i/axi_pcie_0/inst/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT3]] -max 2.000 [get_pins {eth_gmac_top_u/eth_redu_phy_u/gig_ethernet_pcs_pma_0_support_u/phy_gmii_rx_dv[*]}]
set_input_delay -clock [get_clocks -of_objects [get_pins axi_pcie_0_i/pcie_slave_i/axi_pcie_0/inst/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT3]] -min -1.000 [get_pins {eth_gmac_top_u/eth_redu_phy_u/gig_ethernet_pcs_pma_0_support_u/phy_gmii_rx_dv[*]}]

set_output_delay -clock [get_clocks -of_objects [get_pins axi_pcie_0_i/pcie_slave_i/axi_pcie_0/inst/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT3]] -max 2.000 [get_pins {eth_gmac_top_u/eth_redu_phy_u/gig_ethernet_pcs_pma_0_support_u/phy_gmii_txd[*]}]
set_output_delay -clock [get_clocks -of_objects [get_pins axi_pcie_0_i/pcie_slave_i/axi_pcie_0/inst/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT3]] -min -1.000 [get_pins {eth_gmac_top_u/eth_redu_phy_u/gig_ethernet_pcs_pma_0_support_u/phy_gmii_txd[*]}]
set_output_delay -clock [get_clocks -of_objects [get_pins axi_pcie_0_i/pcie_slave_i/axi_pcie_0/inst/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT3]] -max 2.000 [get_pins {eth_gmac_top_u/eth_redu_phy_u/gig_ethernet_pcs_pma_0_support_u/phy_gmii_tx_en[*]}]
set_output_delay -clock [get_clocks -of_objects [get_pins axi_pcie_0_i/pcie_slave_i/axi_pcie_0/inst/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT3]] -min -1.000 [get_pins {eth_gmac_top_u/eth_redu_phy_u/gig_ethernet_pcs_pma_0_support_u/phy_gmii_tx_en[*]}]
set_output_delay -clock [get_clocks -of_objects [get_pins axi_pcie_0_i/pcie_slave_i/axi_pcie_0/inst/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT3]] -max 2.000 [get_pins {eth_gmac_top_u/eth_redu_phy_u/gig_ethernet_pcs_pma_0_support_u/phy_gmii_tx_er[*]}]
set_output_delay -clock [get_clocks -of_objects [get_pins axi_pcie_0_i/pcie_slave_i/axi_pcie_0/inst/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT3]] -min -1.000 [get_pins {eth_gmac_top_u/eth_redu_phy_u/gig_ethernet_pcs_pma_0_support_u/phy_gmii_tx_er[*]}]

同时此描述文档为pg047

同时以太网秒脉冲为以太网自生产,当需要pps外部秒脉冲守时时需关闭以太网秒脉冲功能.

举例压缩bit和其他约束

set_property LOC IBUFDS_GTE2_X0Y6 [get_cells refclk_ibuf]

#set_clock_groups -asynchronous -group [get_clocks sys_clk_p] -group [get_clocks userclk2]

create_clock -period 10.000 -name sys_clk [get_ports sys_clk_p]

set_property LOC GTXE2_CHANNEL_X0Y12 [get_cells {axi_pcie_0_i/pcie_slave_i/axi_pcie_0/inst/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
set_property PACKAGE_PIN D2 [get_ports {pci_exp_txp[0]}]
set_property LOC GTXE2_CHANNEL_X0Y13 [get_cells {axi_pcie_0_i/pcie_slave_i/axi_pcie_0/inst/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
set_property PACKAGE_PIN C4 [get_ports {pci_exp_txp[1]}]
set_property LOC GTXE2_CHANNEL_X0Y14 [get_cells {axi_pcie_0_i/pcie_slave_i/axi_pcie_0/inst/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
set_property PACKAGE_PIN B2 [get_ports {pci_exp_txp[2]}]
set_property LOC GTXE2_CHANNEL_X0Y15 [get_cells {axi_pcie_0_i/pcie_slave_i/axi_pcie_0/inst/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
set_property PACKAGE_PIN A4 [get_ports {pci_exp_txp[3]}]

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets sys_clk]