1.simulation.bat文件
@echo off
@cls
title FPGA Auto Simulation batch script
echo ModelSim simulation
echo.
echo Press '1' to start tb_pll simulation
echo.
echo Press '2' to start tb_fifo_img simulation
echo.
:input
set INPUT=
set /P INPUT=Type test number: %=%
if "%INPUT%"=="1" goto run1
if "%INPUT%"=="2" goto run2
goto end
:run1
@cls
echo Start tb_pll Simulation;
echo.
echo.
cd testbench/tb_pll
vsim -do "do compile.do"
goto clean_workspace
:run2
@cls
echo Start tb_fifo_img Simulation;
echo.
echo.
cd testbench/tb_fifo_img
vsim -do "do compile.do"
goto clean_workspace
rmdir /S /Q work
del vsim.wlf
del transcript.
:end
1.lattice的do文件
vlib work
vmap work work
#library
#IP
vlog -work work ../../lattice_prj/ipx/clk_wiz_0.v
#SourceCode
#vlog -work work ../../design/*.v
#Testbench
vlog -work work testbench_top.v
vsim -voptargs="+acc" -L ovi_ecp3 -L pmi_work work.testbench_top -novopt
#run -all
2.xilinx的do文件
vlib work
vmap work work
vlog -work work glbl.v
#library
#IP
vlog -work work ../../vivado_prj/k7.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
#SourceCode
#vlog -work work ../../design/*.v
#Testbench
vlog -work work testbench_top.v
vsim -voptargs=+acc -L unisims_ver -L unisim -L work -Lf unisims_ver work.glbl work.testbench_top
#Add signal into wave window
do wave.do
#run -all