ISE 中基于mig IP完成DDR3的循环测试
项目简述
该项目的描述是,FPGA向DDR3芯片写入数据,然后再读出数据,从而验证读写模块的正确性。该项目具有一定的实际意义,就是我们新制作的一块FPGA板卡,最有可能出问题的部分就是DDR芯片,因为DDR的实际属于高速设计,然后我们将对应的循环测试的程序下载进去,验证我们硬件板卡的正确性。通过本项目,我们可以学到ISE MIG的读写DDR3的方法,便可以掌握ISE操作DDR3的操作流程。由于身边没有S6系列的板卡,所以本次实验我们只做modelsim仿真。
本次实验所用到的软件环境:
1、ISE14.7软件开发环境
2、modelsim仿真环境
MIG接口的简单描述
IP的FIFO结构图分别如下:
对于生成的MIG IP核,我们现在对其接口信号做出相应的描述,以便于大家可以充分理解信号的作用,
mig_39_2 # (
.C3_P0_MASK_SIZE (8 ),
.C3_P0_DATA_PORT_SIZE (64 ),
.C3_P1_MASK_SIZE (8 ),
.C3_P1_DATA_PORT_SIZE (64 ),
.DEBUG_EN (0 ),
.C3_MEMCLK_PERIOD (3200 ),
.C3_CALIB_SOFT_IP ("TRUE" ),
.C3_SIMULATION ("TURE" ),
.C3_RST_ACT_LOW (0 ),
.C3_INPUT_CLK_TYPE ("SINGLE_ENDED" ),
.C3_MEM_ADDR_ORDER ("BANK_ROW_COLUMN" ),
.C3_NUM_DQ_PINS (16 ),
.C3_MEM_ADDR_WIDTH (13 ),
.C3_MEM_BANKADDR_WIDTH (3 )
)
u_mig_39_2 (
.c3_sys_clk (c3_sys_clk ),
.c3_sys_rst_i (c3_sys_rst_i ),
.mcb3_dram_dq (mcb3_dram_dq ),
.mcb3_dram_a (mcb3_dram_a ),
.mcb3_dram_ba (mcb3_dram_ba ),
.mcb3_dram_ras_n (mcb3_dram_ras_n ),
.mcb3_dram_cas_n (mcb3_dram_cas_n ),
.mcb3_dram_we_n (mcb3_dram_we_n ),
.mcb3_dram_odt (mcb3_dram_odt ),
.mcb3_dram_cke (mcb3_dram_cke ),
.mcb3_dram_ck (mcb3_dram_ck ),
.mcb3_dram_ck_n (mcb3_dram_ck_n ),
.mcb3_dram_dqs (mcb3_dram_dqs ),
.mcb3_dram_dqs_n (mcb3_dram_dqs_n ),
.mcb3_dram_udqs (mcb3_dram_udqs ), // for X16 parts
.mcb3_dram_udqs_n (mcb3_dram_udqs_n ), // for X16 parts
.mcb3_dram_udm (mcb3_dram_udm ), // for X16 parts
.mcb3_dram_dm (mcb3_dram_dm ),
.mcb3_dram_reset_n (mcb3_dram_reset_n ),
.mcb3_rzq (mcb3_rzq ),
.mcb3_zio (mcb3_zio ),
.c3_clk0 (c3_clk0 ),
.c3_rst0 (c3_rst0 ),
.c3_calib_done (c3_calib_done ),
.c3_p0_cmd_clk (c3_p0_cmd_clk ),
.c3_p0_cmd_en (c3_p0_cmd_en ),
.c3_p0_cmd_instr (c3_p0_cmd_instr ),
.c3_p0_cmd_bl (c3_p0_cmd_bl ),
.c3_p0_cmd_byte_addr (c3_p0_cmd_byte_addr ),
.c3_p0_cmd_empty (c3_p0_cmd_empty ),
.c3_p0_cmd_full (c3_p0_cmd_full ),
.c3_p0_wr_clk (c3_p0_wr_clk ),
.c3_p0_wr_en (c3_p0_wr_en ),
.c3_p0_wr_mask (c3_p0_wr_mask ),
.c3_p0_wr_data (c3_p0_wr_data ),
.c3_p0_wr_full (c3_p0_wr_full ),
.c3_p0_wr_empty (c3_p0_wr_empty ),
.c3_p0_wr_count (c3_p0_wr_count ),
.c3_p0_wr_underrun (c3_p0_wr_underrun ),
.c3_p0_wr_error (c3_p0_wr_error ),
.c3_p0_rd_clk (c3_p0_rd_clk ),
.c3_p0_rd_en (c3_p0_rd_en ),
.c3_p0_rd_data (c3_p0_rd_data ),
.c3_p0_rd_full (c3_p0_rd_full ),
.c3_p0_rd_empty (c3_p0_rd_empty ),
.c3_p0_rd_count (c3_p0_rd_count ),
.c3_p0_rd_overflow (c3_p0_rd_overflow ),
.c3_p0_rd_error (c3_p0_rd_error ),
.c3_p1_cmd_clk (c3_p1_cmd_clk ),
.c3_p1_cmd_en (c3_p1_cmd_en ),
.c3_p1_cmd_instr (c3_p1_cmd_instr ),
.c3_p1_cmd_bl (c3_p1_cmd_bl ),
.c3_p1_cmd_byte_addr (c3_p1_cmd_byte_addr ),
.c3_p1_cmd_empty (c3_p1_cmd_empty ),
.c3_p1_cmd_full (c3_p1_cmd_full ),
.c3_p1_wr_clk (c3_p1_wr_clk ),
.c3_p1_wr_en (c3_p1_wr_en ),
.c3_p1_wr_mask (c3_p1_wr_mask ),
.c3_p1_wr_data (c3_p1_wr_data ),
.c3_p1_wr_full (c3_p1_wr_full ),
.c3_p1_wr_empty (c3_p1_wr_empty ),
.c3_p1_wr_count (c3_p1_wr_count ),
.c3_p1_wr_underrun (c3_p1_wr_underrun ),
.c3_p1_wr_error (c3_p1_wr_error ),
.c3_p1_rd_clk (c3_p1_rd_clk ),
.c3_p1_rd_en (c3_p1_rd_en ),
.c3_p1_rd_data (c3_p1_rd_data ),
.c3_p1_rd_full (c3_p1_rd_full ),
.c3_p1_rd_empty (c3_p1_rd_empty ),
.c3_p1_rd_count (c3_p1_rd_count ),
.c3_p1_rd_overflow (c3_p1_rd_overflow ),
.c3_p1_rd_error (c3_p1_rd_error )
);
查阅技术手册,我们对上面的信号做系列陈述:
因为我们再MIG的设置中选择了P0与P1两个64位读写通道,为了简洁起见,我们只对P0通道的数据信号进行讲解
1、C3_P0_MASK_SIZE:设置掩码的数目,一般是数据位宽的字节数
2、C3_P0_DATA_PORT_SIZE:MIG读写通信数据的位宽
3、DEBUG_EN:MIG的debug信号,我们不使用它的debug,想调试自己设置ila进行调试,一般设置为0
4、C3_MEMCLK_PERIOD:MIG IP工作的时钟周期3200ps
5、C3_CALIB_SOFT_IP:与DDR的初始化完成有关,选择TURE
6、C3_SIMULATION :仿真的时候选择TURE,下板的时候选择false即可
7、RST_ACT_LOW:1为MIG IP低复位,0为MIG IP高复位
8、C3_INPUT_CLK_TYPE:输入时钟,我们这里选择单端信号
9、C3_MEM_ADDR_ORDER:MIG中的地址与DDR硬件地址的对应
10、C3_NUM_DQ_PINS:DDR芯片数据位的数目
11、C3_MEM_ADDR_WIDTH:DDR芯片地址的位宽
12、C3_MEM_BANKADDR_WIDTH :DDR芯片bank的数目
上面的设置都与我们上篇文章中MIG的设置有关
13、c3_sys_clk:系统的参考时钟
14、c3_sys_rst_i:MIG对应的复位信号
15、所有带mcb的信号都是与DDR硬件连接的信号,具体含义参考DDR的数据手册,相信如果大家学过SDRAM控制器,对下面的信号很熟悉:
mcb3_dram_dq
mcb3_dram_a
mcb3_dram_ba
mcb3_dram_ras_n
mcb3_dram_cas_n
mcb3_dram_we_n
mcb3_dram_odt
mcb3_dram_cke
mcb3_dram_ck
mcb3_dram_ck_n
mcb3_dram_dqs
mcb3_dram_dqs_n
mcb3_dram_udqs
mcb3_dram_udqs_n
mcb3_dram_udm
mcb3_dram_dm
mcb3_dram_reset_n
mcb3_rzq
mcb3_zio
16、c3_clk0 :MIG给用户提供的时钟,可用可不用,但是vivado中相应的时钟必须使用同步
17、c3_rst0:MIG给用户提供的复位,可用可不用,但是vivado中相应的复位必须使用同步
18、c3_calib_done:MIG自我配置成功之后,该信号拉高,对DDR的操