功能：在ddr中写入一个数，然后读出来
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:13:21 09/20/2019
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top(
input clk_50m,
input reset_n,
output [1:0] led, //led灯指示
//DDR的接口信号
inout [15:0] mcb3_dram_dq,
output [12:0] mcb3_dram_a,
output [2:0] mcb3_dram_ba,
output mcb3_dram_ras_n,
output mcb3_dram_cas_n,
output mcb3_dram_we_n,
output mcb3_dram_odt,
output mcb3_dram_reset_n,
output mcb3_dram_cke,
output mcb3_dram_dm,
inout mcb3_dram_udqs,
inout mcb3_dram_udqs_n,
inout mcb3_rzq,
inout mcb3_zio,
output mcb3_dram_udm,
inout mcb3_dram_dqs,
inout mcb3_dram_dqs_n,
output mcb3_dram_ck,
output mcb3_dram_ck_n
);
assign led = 2'd3;
//DDR读写控制部分
ddr_rw ddr_rw_inst(
.mcb3_dram_dq (mcb3_dram_dq),
.mcb3_dram_a (mcb3_dram_a),
.mcb3_dram_ba (mcb3_dram_ba),
.mcb3_dram_ras_n (mcb3_dram_ras_n),
.mcb3_dram_cas_n (mcb3_dram_cas_n),
.mcb3_dram_we_n (mcb3_dram_we_n),
.mcb3_dram_odt (mcb3_dram_odt),
.mcb3_dram_reset_n (mcb3_dram_reset_n),
.mcb3_dram_cke (mcb3_dram_cke),
.mcb3_dram_dm (mcb3_dram_dm),
.mcb3_dram_udqs (mcb3_dram_udqs),
.mcb3_dram_udqs_n (mcb3_dram_udqs_n),
.mcb3_rzq (mcb3_rzq),
.mcb3_zio (mcb3_zio),
.mcb3_dram_udm (mcb3_dram_udm),
.c3_sys_clk (clk_50m),
.c3_sys_rst_n (reset_n),
.mcb3_dram_dqs (mcb3_dram_dqs),
.mcb3_dram_dqs_n (mcb3_dram_dqs_n),
.mcb3_dram_ck (mcb3_dram_ck),
.mcb3_dram_ck_n (mcb3_dram_ck_n)
);
endmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name: ddr_rw
//////////////////////////////////////////////////////////////////////////////////
module ddr_rw #
(
parameter C3_NUM_DQ_PINS = 16, // External memory data width
parameter C3_MEM_ADDR_WIDTH = 13, // External memory address width
parameter C3_MEM_BANKADDR_WIDTH = 3 // External memory bank address width
)
(
//DDR的接口信号
inout [C3_NUM_DQ_PINS-1:0] mcb3_dram_dq,
output [C3_MEM_ADDR_WIDTH-1:0] mcb3_dram_a,
output [C3_MEM_BANKADDR_WIDTH-1:0] mcb3_dram_ba,
output mcb3_dram_ras_n,
output mcb3_dram_cas_n,
output mcb3_dram_we_n,
output mcb3_dram_odt,
output mcb3_dram_reset_n,
output mcb3_dram_cke,
output mcb3_dram_dm,
inout mcb3_dram_udqs,
inout mcb3_dram_udqs_n,
inout mcb3_rzq,
inout mcb3_zio,
output mcb3_dram_udm,
input c3_sys_clk,
input c3_sys_rst_n,
inout mcb3_dram_dqs,
inout mcb3_dram_dqs_n,
output mcb3_dram_ck,
output mcb3_dram_ck_n
);
wire c3_clk0;
wire c3_rst0;
wire c3_calib_done;
reg [3:0] ddr_write_state;
reg [63:0] rd_data;
reg c3_p0_wr_en;
reg [7:0] c3_p0_wr_mask;
reg c3_p0_cmd_en;
reg c3_p1_cmd_en;
reg c3_p1_rd_en;
wire c3_p0_wr_full;
reg [63:0] c3_p0_wr_data;
wire c3_p0_cmd_full;
reg [2:0] c3_p0_cmd_instr;
reg [5:0] c3_p0_cmd_bl;
wire c3_p1_cmd_empty;
reg [2:0] c3_p1_cmd_instr;
reg [5:0] c3_p1_cmd_bl;
wire c3_p1_rd_empty;
wire [63:0] c3_p1_rd_data;
reg [29:0] c3_p0_cmd_byte_addr;
reg [29:0] c3_p1_cmd_byte_addr;
wire c3_p0_cmd_clk;
wire c3_p0_rd_clk;
wire c3_p0_wr_clk;
wire c3_p1_cmd_clk;
wire c3_p1_wr_clk;
wire c3_p1_rd_clk;
assign c3_p0_cmd_clk = c3_clk0;
assign c3_p0_rd_clk = c3_clk0;
assign c3_p0_wr_clk = c3_clk0;
assign c3_p1_cmd_clk = c3_clk0;
assign c3_p1_wr_clk = c3_clk0;
assign c3_p1_rd_clk = c3_clk0;
always @(posedge c3_clk0)
begin
if(c3_rst0 || !c3_calib_done) begin
ddr_write_state<=4'd0;
c3_p0_wr_en<=1'b0;
c3_p0_wr_mask<=8'd0;
c3_p0_cmd_en<=1'b0;
c3_p1_cmd_en<=1'b0;
c3_p1_rd_en<=1'b0;
c3_p1_cmd_byte_addr<=30'd0;
c3_p0_cmd_byte_addr<=30'd0;
end
else begin
case(ddr_write_state)
4'd0: begin
if(!c3_p0_wr_full) begin
c3_p0_wr_en<=1'b1;
c3_p0_wr_mask<=8'd0;
c3_p0_wr_data<=64'h12345678;
ddr_write_state <= ddr_write_state + 4'd1;
end
end
4'd1: begin
c3_p0_wr_en<=1'b0;
ddr_write_state <= ddr_write_state + 4'd1;
end
4'd2: begin
if(!c3_p0_cmd_full) begin
c3_p0_cmd_en<=1'b1;
c3_p0_cmd_instr<=3'b010; //010为写命令
c3_p0_cmd_bl<=6'd0; //burst length为1个64bit宽的数据
ddr_write_state <= ddr_write_state + 4'd1;
end
end
4'd3: begin
c3_p0_cmd_en<=1'b0;
ddr_write_state <= ddr_write_state + 4'd1;
end
4'd4: begin
c3_p1_cmd_en<=1'b1;
c3_p1_cmd_instr<=3'b001; //命令字为读
c3_p1_cmd_bl<=6'd0; //single read
ddr_write_state <= ddr_write_state + 4'd1;
end
4'd5: begin
c3_p1_cmd_en<=1'b0;
if(!c3_p1_rd_empty) begin
c3_p1_rd_en<=1'b1;
ddr_write_state <= ddr_write_state + 4'd1;
rd_data <= c3_p1_rd_data;
end
end
4'd6: begin
c3_p1_rd_en<=1'b0;
ddr_write_state <= ddr_write_state + 4'd1;
end
endcase
end
end
// MIG的DDR控制器程序例化
ddr3 #
(
.C3_P0_MASK_SIZE (8),
.C3_P0_DATA_PORT_SIZE (64),
.C3_P1_MASK_SIZE (8),
.C3_P1_DATA_PORT_SIZE (64),
.DEBUG_EN (0), // = 0, Disable debug signals/controls.
.C3_MEMCLK_PERIOD (3200),
.C3_CALIB_SOFT_IP ("TRUE"), // # = TRUE, Enables the soft calibration logic,
.C3_SIMULATION ("FALSE"), // # = FALSE, Implementing the design.
.C3_RST_ACT_LOW (1), // # = 1 for active low reset change for AX516 board
.C3_INPUT_CLK_TYPE ("SINGLE_ENDED"),
.C3_MEM_ADDR_ORDER ("ROW_BANK_COLUMN"),
.C3_NUM_DQ_PINS (16),
.C3_MEM_ADDR_WIDTH (15),
.C3_MEM_BANKADDR_WIDTH (3)
)
ddr3_inst
(
.mcb3_dram_dq (mcb3_dram_dq),
.mcb3_dram_a (mcb3_dram_a),
.mcb3_dram_ba (mcb3_dram_ba),
.mcb3_dram_ras_n (mcb3_dram_ras_n),
.mcb3_dram_cas_n (mcb3_dram_cas_n),
.mcb3_dram_we_n (mcb3_dram_we_n),
.mcb3_dram_reset_n (mcb3_dram_reset_n),
.mcb3_dram_odt (mcb3_dram_odt),
.mcb3_dram_cke (mcb3_dram_cke),
.mcb3_dram_dm (mcb3_dram_dm),
.mcb3_dram_udqs (mcb3_dram_udqs),
.mcb3_dram_udqs_n (mcb3_dram_udqs_n),
.mcb3_rzq (mcb3_rzq),
.mcb3_zio (mcb3_zio),
.mcb3_dram_udm (mcb3_dram_udm),
.c3_sys_clk (c3_sys_clk),
.c3_sys_rst_i (c3_sys_rst_n),
.c3_calib_done (c3_calib_done),
.c3_clk0 (c3_clk0),
.c3_rst0 (c3_rst0),
.mcb3_dram_dqs (mcb3_dram_dqs),
.mcb3_dram_dqs_n (mcb3_dram_dqs_n),
.mcb3_dram_ck (mcb3_dram_ck),
.mcb3_dram_ck_n (mcb3_dram_ck_n),
// User Port-0 command interface
.c3_p0_cmd_clk (c3_clk0), //c3_p0_cmd_clk->c3_clk0
.c3_p0_cmd_en (c3_p0_cmd_en),
.c3_p0_cmd_instr (c3_p0_cmd_instr),
.c3_p0_cmd_bl (c3_p0_cmd_bl),
.c3_p0_cmd_byte_addr (c3_p0_cmd_byte_addr),
.c3_p0_cmd_empty (c3_p0_cmd_empty),
.c3_p0_cmd_full (c3_p0_cmd_full),
// User Port-0 data write interface
.c3_p0_wr_clk (c3_clk0), //c3_p0_wr_clk->c3_clk0
.c3_p0_wr_en (c3_p0_wr_en),
.c3_p0_wr_mask (c3_p0_wr_mask),
.c3_p0_wr_data (c3_p0_wr_data),
.c3_p0_wr_full (c3_p0_wr_full),
.c3_p0_wr_empty (c3_p0_wr_empty),
.c3_p0_wr_count (c3_p0_wr_count),
.c3_p0_wr_underrun (c3_p0_wr_underrun),
.c3_p0_wr_error (c3_p0_wr_error),
// User Port-0 data read interface
.c3_p0_rd_clk (c3_clk0), //c3_p0_rd_clk->c3_clk0
.c3_p0_rd_en (c3_p0_rd_en),
.c3_p0_rd_data (c3_p0_rd_data),
.c3_p0_rd_full (c3_p0_rd_full),
.c3_p0_rd_empty (c3_p0_rd_empty),
.c3_p0_rd_count (c3_p0_rd_count),
.c3_p0_rd_overflow (c3_p0_rd_overflow),
.c3_p0_rd_error (c3_p0_rd_error),
// User Port-1 command interface
.c3_p1_cmd_clk (c3_clk0), //c3_p1_cmd_clk->c3_clk0
.c3_p1_cmd_en (c3_p1_cmd_en),
.c3_p1_cmd_instr (c3_p1_cmd_instr),
.c3_p1_cmd_bl (c3_p1_cmd_bl),
.c3_p1_cmd_byte_addr (c3_p1_cmd_byte_addr),
.c3_p1_cmd_empty (c3_p1_cmd_empty),
.c3_p1_cmd_full (c3_p1_cmd_full),
// User Port-1 data write interface
.c3_p1_wr_clk (c3_clk0), //c3_p1_wr_clk->c3_clk0
.c3_p1_wr_en (c3_p1_wr_en),
.c3_p1_wr_mask (c3_p1_wr_mask),
.c3_p1_wr_data (c3_p1_wr_data),
.c3_p1_wr_full (c3_p1_wr_full),
.c3_p1_wr_empty (c3_p1_wr_empty),
.c3_p1_wr_count (c3_p1_wr_count),
.c3_p1_wr_underrun (c3_p1_wr_underrun),
.c3_p1_wr_error (c3_p1_wr_error),
// User Port-1 data read interface
.c3_p1_rd_clk (c3_clk0), //c3_p1_rd_clk->c3_clk0
.c3_p1_rd_en (c3_p1_rd_en),
.c3_p1_rd_data (c3_p1_rd_data),
.c3_p1_rd_full (c3_p1_rd_full),
.c3_p1_rd_empty (c3_p1_rd_empty),
.c3_p1_rd_count (c3_p1_rd_count),
.c3_p1_rd_overflow (c3_p1_rd_overflow),
.c3_p1_rd_error (c3_p1_rd_error)
);
endmodule
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:38:27 09/25/2019
// Design Name: top
// Module Name: E:/ZJQ/temp/ax516/ise/top/vtf_top.v
// Project Name: top
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module vtf_top;
// Inputs
reg clk_50m;
reg reset_n;
// Outputs
wire [1:0] led;
wire [12:0] mcb3_dram_a;
wire [2:0] mcb3_dram_ba;
wire mcb3_dram_ras_n;
wire mcb3_dram_cas_n;
wire mcb3_dram_we_n;
wire mcb3_dram_odt;
wire mcb3_dram_reset_n;
wire mcb3_dram_cke;
wire mcb3_dram_dm;
wire mcb3_dram_udm;
wire mcb3_dram_ck;
wire mcb3_dram_ck_n;
// Bidirs
wire [15:0] mcb3_dram_dq;
wire mcb3_dram_udqs;
wire mcb3_dram_udqs_n;
wire mcb3_rzq;
wire mcb3_zio;
wire mcb3_dram_dqs;
wire mcb3_dram_dqs_n;
// Instantiate the Unit Under Test (UUT)
top uut (
.clk_50m(clk_50m),
.reset_n(reset_n),
.led(led),
.mcb3_dram_dq(mcb3_dram_dq),
.mcb3_dram_a(mcb3_dram_a),
.mcb3_dram_ba(mcb3_dram_ba),
.mcb3_dram_ras_n(mcb3_dram_ras_n),
.mcb3_dram_cas_n(mcb3_dram_cas_n),
.mcb3_dram_we_n(mcb3_dram_we_n),
.mcb3_dram_odt(mcb3_dram_odt),
.mcb3_dram_reset_n(mcb3_dram_reset_n),
.mcb3_dram_cke(mcb3_dram_cke),
.mcb3_dram_dm(mcb3_dram_dm),
.mcb3_dram_udqs(mcb3_dram_udqs),
.mcb3_dram_udqs_n(mcb3_dram_udqs_n),
.mcb3_rzq(mcb3_rzq),
.mcb3_zio(mcb3_zio),
.mcb3_dram_udm(mcb3_dram_udm),
.mcb3_dram_dqs(mcb3_dram_dqs),
.mcb3_dram_dqs_n(mcb3_dram_dqs_n),
.mcb3_dram_ck(mcb3_dram_ck),
.mcb3_dram_ck_n(mcb3_dram_ck_n)
);
ddr3_model_c3 u_mem_c3(
.ck (mcb3_dram_ck),
.ck_n (mcb3_dram_ck_n),
.cke (mcb3_dram_cke),
.cs_n (1'b0),
.ras_n (mcb3_dram_ras_n),
.cas_n (mcb3_dram_cas_n),
.we_n (mcb3_dram_we_n),
.dm_tdqs ({mcb3_dram_udm,mcb3_dram_dm}),
.ba (mcb3_dram_ba),
.addr (mcb3_dram_a),
.dq (mcb3_dram_dq),
.dqs ({mcb3_dram_udqs,mcb3_dram_dqs}),
.dqs_n ({mcb3_dram_udqs_n,mcb3_dram_dqs_n}),
.tdqs_n (),
.odt (mcb3_dram_odt),
.rst_n (mcb3_dram_reset_n)
);
initial begin
// Initialize Inputs
clk_50m = 0;
reset_n = 0;
// Wait 100 ns for global reset to finish
#100;
reset_n = 1;
// Add stimulus here
end
always #10 clk_50m = ~clk_50m;
endmodule
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