一、定时器代码
module freq_tim (
input clk,
input rstn,
output [4:0] hour,
output [5:0] min,
output [5:0] sec
);
parameter CLK_TIM = 60;
parameter CLK_HOUR = 24;
reg [5:0] idc = 6'b0;
reg [5:0] idc_min = 6'b0;
reg [5:0] idc_sec = 6'b0;
reg [4:0] idc_hour = 6'b0;
assign sec = idc_sec;
assign min = idc_min;
assign hour = idc_hour;
always @(posedge clk or negedge rstn) begin
if (!rstn)
idc <= 1'b0;
else if (idc == 60)
idc <= 1'b0;
else
idc <= idc + 1'b1;
end
always @(posedge clk or negedge rstn) begin
if (!rstn)
idc_sec <= 1'b0;
else if (idc_sec == CLK_TIM)
idc_sec <= 1'b0;
else if (idc == 60)
idc_sec <= idc_sec + 1'b1;
else
idc_sec <= idc_sec;
end
always @(posedge clk or negedge rstn) begin
if (!rstn)
idc_min <= 1'b0;
else if (idc_min == CLK_TIM)
idc_min <= 1'b0;
else if (idc_sec == CLK_TIM)
idc_min <= idc_min + 1'b1;
else
idc_min <= idc_min;
end
always @(posedge clk or negedge rstn) begin
if (!rstn)
idc_hour <= 1'b0;
else if (idc_hour == CLK_HOUR)
idc_hour <= 1'b0;
else if (idc_min == CLK_TIM)
idc_hour <= idc_hour + 1'b1;
else
idc_hour <= idc_hour;
end
endmodule
二、测试代码:
`timescale 1ns/1ns
module freq_tim_tb ();
reg clk, rstn;
wire [4:0] hour;
wire [5:0] min, sec;
freq_tim #(.CLK_TIM(60),.CLK_HOUR(12))
tim(
.clk(clk),
.rstn(rstn),
.hour(hour),
.min(min),
.sec(sec)
);
initial clk = 1'b0;
always #5 clk = ~clk;
initial begin
$dumpfile("freq_tim_tb.vcd");
$dumpvars;
rstn = 0;
#10
rstn = 1;
#20_000_000
$stop;
end
endmodule
三、生成的波形: