一、计数器代码:
module counter (
input clk,
input rstn,
output [5:0] cn1,
output [5:0] cn2,
output [5:0] cn3
);
parameter CLK_CNT = 5;
parameter CLK_END = CLK_CNT-1;
reg [5:0] ida = 6'b0;
reg [5:0] idc = 6'b0;
reg [5:0] idd = 6'b0;
assign cn1 = ida;
assign cn2 = idc;
assign cn3 = idd;
always @(posedge clk or negedge rstn) begin
if (!rstn)
ida <= 1'b0;
else if (ida == CLK_END)
ida <= 1'b0;
else
ida <= ida + 1'b1;
end
always @(posedge clk or negedge rstn) begin
if (!rstn)
idc <= 1'b0;
else if (idc == CLK_END)
idc <= 1'b0;
else if (ida == CLK_END)
idc <= idc + 1'b1;
else
idc <= idc;
end
always @(posedge clk or negedge rstn) begin
if (!rstn)
idd <= 1'b0;
else if (idd == 11)
idd <= 1'b0;
else if (idc == CLK_END)
idd <= idd + 1'b1;
else
idd <= idd;
end
endmodule
二、测试代码:
`timescale 1ns/1ns
module counter_tb ();
reg clk, rstn;
wire [5:0] cn1, cn2, cn3;
counter #(.CLK_CNT(5))
u_counter(
.clk(clk),
.rstn(rstn),
.cn1(cn1),
.cn2(cn2),
.cn3(cn3)
);
initial clk = 1'b0;
always #5 clk = ~clk;
initial begin
$dumpfile("counter_tb.vcd");
$dumpvars;
rstn = 0;
#10
rstn = 1;
#10_000_000
$stop;
end
endmodule
三、波形输出