状态机设计实例-优快云博客

本文链接：https://blog.youkuaiyun.com/whywhatwhenhow/article/details/4700093

本文介绍了一个使用VHDL实现的状态机设计案例，包括状态定义、信号声明及两个进程的详细逻辑，展示了如何通过状态转移实现特定功能。

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity zhuantaiji is
    Port ( clk : in std_logic;
       rst : in std_logic;
           wave : out std_logic := '0');
--           reset : in std_logic);
end zhuantaiji;

architecture Behavioral of zhuantaiji is
type state is(state_init,state0, state1, state2,state3,state4,state5,state6,state7);
signal pr_state, nx_state: state := state_init;  --ÎªÊ²Ã´´Ë´¦¶¨ÒåÎªÐÅºÅ
signal tmp : std_logic;
begin
process(rst,clk)
begin
if(rst = '1')then
  pr_state <= state_init;
  wave <= '0';
  elsif(clk'event and clk = '1')then
  wave <= tmp;
  pr_state <= nx_state;
end if;
end process;

process (pr_state)
begin
  case pr_state is
  when state_init =>

     tmp <= '0';
     nx_state <= state0;

   when state0 =>

     tmp <= '1';
     nx_state <= state1;

when state1 =>

tmp <= '0';
nx_state <= state2;

   when state2 =>

     tmp <= '1';
     nx_state <= state3;

   when state3 =>

     tmp <= '1';
     nx_state <= state4;

   when state4 =>

     tmp <= '1';
     nx_state <= state5;

   when state5 =>

     tmp <= '0';
     nx_state <= state6;

   when state6 =>

     tmp <= '0';
     nx_state <= state7;

   when state7 =>
  --  null;
  --  if(clk = '1') then
  --   wave <= 0;
  --   pr_state <= state2;
  --  end if;
  end case;
end process;
end Behavioral;