采用风格2的信号发生器

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity zhuantaiji is
    Port ( clk : in std_logic;
       rst : in std_logic;
           wave : out std_logic := '0');
--           reset : in std_logic);
end zhuantaiji;

architecture Behavioral of zhuantaiji is
 type state is(state_init,state0, state1, state2,state3,state4,state5,state6,state7);
 signal pr_state, nx_state: state := state_init;  --Ϊʲô´Ë´¦¶¨ÒåΪÐźÅ
 signal tmp : std_logic;
begin
 process(rst,clk)
 begin
 if(rst = '1')then
  pr_state <= state_init;
  wave <= '0';
  elsif(clk'event and clk = '1')then
  wave <= tmp;
  pr_state <= nx_state;
 end if;
 end process;

 process (pr_state)
 begin
  case pr_state is
  when state_init =>
   
     tmp <= '0';
     nx_state <= state0;
 
   when state0 =>
 
     tmp <= '1';
     nx_state <= state1;

      when state1 =>

     tmp <= '0';
     nx_state <= state2;

   when state2 =>
   
     tmp <= '1';
     nx_state <= state3;
   
   when state3 =>
  
     tmp <= '1';
     nx_state <= state4;
   
   when state4 =>
  
     tmp <= '1';
     nx_state <= state5;
   
   when state5 =>
  
     tmp <= '0';
     nx_state <= state6;
  
   when state6 =>
   
     tmp <= '0';
     nx_state <= state7;
  
   when state7 =>
  --  null;
  --  if(clk = '1') then
  --   wave <= 0;
  --   pr_state <= state2;
  --  end if;
  end case;
 end process;
end Behavioral;