LED循环电路在 basys-3 上实现

最新推荐文章于 2023-07-25 12:21:07 发布

原创最新推荐文章于 2023-07-25 12:21:07 发布 · 341 阅读

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CC 4.0 BY-SA版权

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#fpga开发 #单片机 #嵌入式硬件

该代码描述了一个Verilog设计，包括auto_circulate和LED_circulate_display模块，用于根据输入的开关值循环改变LED显示。CLK_to_clk模块提供了一个时钟分频器。主模块top_circulate_LED连接这些组件并处理输入和输出。设计中使用了状态机来切换LED显示的数字。

在这里插入图片描述


module auto_circulate(
    input CLK,rst,
    output [3:0]SW_in
);
    wire clk;
    CLK_to_clk #(100000000) clock1  (CLK,rst,clk);
    reg [3:0]t ;
    always@(posedge clk,posedge rst)
    begin
        if(rst)
            t<=0;
        else
        begin
            if(t<10)
                t<=t+1;
            else
                t<=0;
        end
    end
    assign SW_in = t;

endmodule


module LED_circulate_display(
    input CLK,rst,
    input [3:0]SW_in, // 输入一个十进制数，显示会相应变化
    output reg [10:0]display_out
);
reg [19:0]count=0; 
reg [2:0] sel=0; 
parameter T1MS=5000; 



always@(posedge CLK) 
    begin 
        if(SW_in==4'd0) 
         begin 
             case(sel) 
             0:display_out<=11'b0111_0000001;  //0
             1:display_out<=11'b1011_1001111;  //1
             2:display_out<=11'b1101_0010010;  //2
             3:display_out<=11'b1110_0000110;  //3
             default:display_out<=11'b1111_1111111; 
             endcase 
         end 
         else if(SW_in==4'd1) 
         begin 
             case(sel) 
             0:display_out<=11'b0111_1001111;  //1
             1:display_out<=11'b1011_0010010;  //2
             2:display_out<=11'b1101_0000110;  //3
             3:display_out<=11'b1110_1001100;  //4
             default:display_out<=11'b1111_1111111; 
             endcase 
         end 
         else if(SW_in==4'd2) 
         begin 
            case(sel) 
             0:display_out<=11'b0111_0010010;  //2
             1:display_out<=11'b1011_0000110;  //3
             2:display_out<=11'b1101_1001100;  //4
             3:display_out<=11'b1110_0100100;  //5
             default:display_out<=11'b1111_1111111; 
             endcase 
         end 
         else if(SW_in==4'd3) 
         begin 
            case(sel) 
             0:display_out<=11'b0111_0000110;  //3
             1:display_out<=11'b1011_1001100;  //4
             2:display_out<=11'b1101_0100100;  //5
             3:display_out<=11'b1110_0100000;  //6
             default:display_out<=11'b1111_1111111; 
             endcase 
         end 
         else if(SW_in==4'd4) 
         begin 
            case(sel) 
             0:display_out<=11'b0111_1001100;  //4
             1:display_out<=11'b1011_0100100;  //5
             2:display_out<=11'b1101_0100000;  //6
             3:display_out<=11'b1110_0001111;  //7
             default:display_out<=11'b1111_1111111; 
             endcase 
         end 
         else if(SW_in==4'd5) 
         begin 
            case(sel) 
             0:display_out<=11'b0111_0100100;  //5
             1:display_out<=11'b1011_0100000;  //6
             2:display_out<=11'b1101_0001111;  //7
             3:display_out<=11'b1110_0000000;  //8
             default:display_out<=11'b1111_1111111; 
             endcase 
         end 
         else if(SW_in==4'd6) 
         begin 
            case(sel) 
             0:display_out<=11'b0111_0100000;  //6
             1:display_out<=11'b1011_0001111;  //7
             2:display_out<=11'b1101_0000000;  //8
             3:display_out<=11'b1110_0000100;  //9
             default:display_out<=11'b1111_1111111; 
             endcase 
         end
         else if(SW_in==4'd7) 
         begin 
            case(sel) 
             0:display_out<=11'b0111_0001111;  //7
             1:display_out<=11'b1011_0000000;  //8
             2:display_out<=11'b1101_0000100;  //9
             3:display_out<=11'b1110_0000001;  //0
             default:display_out<=11'b1111_1111111; 
             endcase 
         end
          else if(SW_in==4'd8) 
         begin 
            case(sel) 
             0:display_out<=11'b0111_0000000;  //8
             1:display_out<=11'b1011_0000100;  //9
             2:display_out<=11'b1101_0000001;  //0
             3:display_out<=11'b1110_1001111;  //1
             default:display_out<=11'b1111_1111111; 
             endcase 
         end
         else if(SW_in==4'd9) 
         begin 
            case(sel) 
             0:display_out<=11'b0111_0000100;  //9
             1:display_out<=11'b1011_0000001;  //0
             2:display_out<=11'b1101_1001111;  //1
             3:display_out<=11'b1110_0010010;  //2
             default:display_out<=11'b1111_1111111; 
             endcase 
         end
         else 
             display_out<=11'b1111_1111111; 

    end 
    
always@(posedge CLK) 
 begin 
     count<=count+1; 
     if(count==T1MS) 
     begin 
         count<=0; 
         sel<=sel+1; 
         if(sel==4) 
         sel<=0; 
     end 
end
endmodule

module top_circulate_LED(
    input CLK,rst,
    input en,
    input [3:0]SW_in,
    output [10:0]display_out
);
    wire [3:0]SW_in_auto;
    wire [3:0]SW;
    assign SW = (en==1)?SW_in_auto:SW_in;
    auto_circulate auto(
        .CLK(CLK),
        .rst(rst),
        .SW_in(SW_in_auto)
    );
    LED_circulate_display show_circulate (
        .CLK(CLK),
        .rst(rst),
        .SW_in(SW),
        .display_out(display_out)
    );
endmodule

module CLK_to_clk
#(parameter T1MS = 7500000) 
(
    input CLK,rst,
    output clk
);
    reg [32:0]count;
    always @(posedge CLK,posedge rst)
    begin
        if(rst)
            count<=0;
        else 
        begin 
            if(count < T1MS)
                count<= count+1 ;
            else count <= 0;
        end
    end
    assign clk = (count==T1MS)?1:0;
endmodule

约束文件

set_property PACKAGE_PIN W5 [get_ports CLK] 
set_property PACKAGE_PIN T18 [get_ports rst] 
set_property PACKAGE_PIN W15 [get_ports en] 
set_property PACKAGE_PIN V17 [get_ports SW_in[0]] 
set_property PACKAGE_PIN V16 [get_ports SW_in[1]] 
set_property PACKAGE_PIN W16 [get_ports SW_in[2]] 
set_property PACKAGE_PIN W17 [get_ports SW_in[3]] 
set_property IOSTANDARD LVCMOS33 [get_ports SW_in[0]]
set_property IOSTANDARD LVCMOS33 [get_ports SW_in[1]]  
set_property IOSTANDARD LVCMOS33 [get_ports SW_in[2]]
set_property IOSTANDARD LVCMOS33 [get_ports SW_in[3]]
set_property IOSTANDARD LVCMOS33 [get_ports en]
set_property IOSTANDARD LVCMOS33 [get_ports rst]    
set_property IOSTANDARD LVCMOS33 [get_ports CLK] 
set_property PACKAGE_PIN W4 [get_ports {display_out[10]}] 
set_property PACKAGE_PIN V4 [get_ports {display_out[9]}] 
set_property PACKAGE_PIN U4 [get_ports {display_out[8]}] 
set_property PACKAGE_PIN U2 [get_ports {display_out[7]}] 
set_property PACKAGE_PIN W7 [get_ports {display_out[6]}] 
set_property PACKAGE_PIN W6 [get_ports {display_out[5]}] 
set_property PACKAGE_PIN U8 [get_ports {display_out[4]}] 
set_property PACKAGE_PIN V8 [get_ports {display_out[3]}] 
set_property PACKAGE_PIN U5 [get_ports {display_out[2]}] 
set_property PACKAGE_PIN V5 [get_ports {display_out[1]}] 
set_property PACKAGE_PIN U7 [get_ports {display_out[0]}] 
set_property IOSTANDARD LVCMOS33 [get_ports {display_out[9]}] 
set_property IOSTANDARD LVCMOS33 [get_ports {display_out[8]}] 
set_property IOSTANDARD LVCMOS33 [get_ports {display_out[7]}] 
set_property IOSTANDARD LVCMOS33 [get_ports {display_out[6]}] 
set_property IOSTANDARD LVCMOS33 [get_ports {display_out[5]}] 
set_property IOSTANDARD LVCMOS33 [get_ports {display_out[4]}] 
set_property IOSTANDARD LVCMOS33 [get_ports {display_out[3]}] 
set_property IOSTANDARD LVCMOS33 [get_ports {display_out[1]}] 
set_property IOSTANDARD LVCMOS33 [get_ports {display_out[2]}] 
set_property IOSTANDARD LVCMOS33 [get_ports {display_out[0]}] 
set_property IOSTANDARD LVCMOS33 [get_ports {display_out[10]}]