备战秋招之Verilog序列检测器代码

检测10010序列

module dec(

input data,clk,rat_n,
output reg result

);

reg [4:0] curr_st,next_st;
parameter    S_IDLE = 5'b00000;
parameter        S1 = 5'b00001;
parameter       S10 = 5'b00010;
parameter      S100 = 5'b00100;
parameter     S1001 = 5'b01000;
parameter    S10010 = 5'b10000;

//描述状态转移
always @(posedge clk or negedge rst_n)begin
    if (!rst_n)
        curr_st <= S_IDLE;
    else
        curr_st <= next_st;

//描述转移条件
always @(*)begin
    if(!rst_n)begin
        next = S_IDLE;
    end
    else begin
        case(curr_st)
        S_IDLE: if(date == 1)  next_st = S1 ;
                else           next_st = S_IDLE  ;
        S1 :    if(date == 0)  next_st = S10 ;
                else           next_st = S1 ;
        S10 :    if(date == 0)  next_st = S100 ;
                else           next_st = S1 ;
        S100 :    if(date == 1)  next_st = S1001 ;
                else           next_st = S_IDLE  ;
        S1001 :    if(date == 0)  next_st = S10010 ;
                else           next_st = S1 ;
        S10010 :    if(date == 0)  next_st = S100 ;
                else           next_st = S1 ;
        default: next_st = S_IDLE;
        endcase
    end
end

//描述输出
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        result <= 1'b0;
    end
    else begin
        case(curr_st)
        S5:        result <= 1'b1;
        default:   result <= 1'b0;
        endcase
    end
end

endmoudle