一起来学FPGA（vhdl）一：点亮流水灯_ise14.7fpga点灯-优快云博客

本文链接：https://blog.youkuaiyun.com/weixin_39815697/article/details/102535310

环境

软件：ISE 14.7
硬件：ALINX AX309¹

关键逻辑

定时器

以clk为时钟频率，设置一个1s的定时器。

process(clk)
begin
	if(clk'event and clk = '1') then 
		count<=count+1;
		if(count = 50000000) then
			tim <= '1';
			count <= 0;
		else
			tim <= '0';
		end if;
	end if;
end process;

移位操作

语法²³：

<left operand> <shift operation> <right operand>

left operand：必须是BIT_VECTOR
right operand：必须是INTEGER
shift operation：
- sll(Shift left logical)，逻辑左移
- srl(Shift right logical)，逻辑右移
- sla(Shift left arithmetic)，算术左移
- srl(Shift left arithmetic)，算术右移
- rol(Rotate left logical)，逻辑循环左移
- ror(Rotate right logical)，逻辑循环右移

例如：

b <= b rol 1;

tim为定时器触发信号，以该信号作为流水灯的频率，tim上升沿触发，每次触发都将进行循环移位操作(rol)，实现流水灯效果。

process(tim)
begin
	if(tim'event and tim = '1') then 
		b <= b rol 1;
		leds <= b;
	end if;
end process;

Concatenation “&”

Description
The concatenation operator (denoted as &) composes two one-dimensional arrays into a larger one of the same type. A single element can be used as any of the two operands of concatenation. If two single elements are concatenated, then the result can be of any array type (as long as it is compatible with the type of the operands).

The resulting array is composed of the elements of the left operand (in left-to-right order) followed by the elements of the right operand (in the same order). The direction of the resulting array is the same as of the left operand, unless the left operand is a null array, in which case the direction of the result is that of the right operand.⁴
例如：

b <= b(2 downto 0) & 1;

假设b=“0001”，则每次将后三位与第一位相连接，也可以实现移位效果。

process(tim)
begin
	if(tim'event and tim = '1') then 
		b <= b(2 downto 0) & b(3);
	end if;
end process;

Code1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity LoopLEDs is
	Port(clk : in bit;
		 leds: out bit_vector(3 downto 0):="0000");
end LoopLEDs;

architecture Behavioral of LoopLEDs is
signal b:bit_vector(3 downto 0):="0001";
signal count:integer:=0;
signal tim:bit:='0';
begin
	process(clk)
	begin
		if(clk'event and clk = '1') then 
			count<=count+1;
			if(count = 50000000) then
				tim <= '1';
				count <= 0;
			else
				tim <= '0';
			end if;
		end if;
	end process;
	
	process(tim)
	begin
		if(tim'event and tim = '1') then 
			b <= b rol 1;
		end if;
	end process;
	leds <= b;
end Behavioral;

Code2

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity LoopLEDs is
	Port(clk : in STD_LOGIC;
		 leds: out STD_LOGIC_VECTOR(3 downto 0):="0000");
end LoopLEDs;

architecture Behavioral of LoopLEDs is
signal b:STD_LOGIC_VECTOR(3 downto 0):="0001";
signal count:integer:=0;
signal tim:bit:='0';
begin
	process(clk)
	begin
		if(clk'event and clk = '1') then 
			count<=count+1;
			if(count = 50000000) then
				tim <= '1';
				count <= 0;
			else
				tim <= '0';
			end if;
		end if;
	end process;
	
	process(tim)
	begin
		if(tim'event and tim = '1') then 
			b <= b(2 downto 0) & b(3);
		end if;
	end process;
	leds <= b;
end Behavioral;

AX309.ucf(节选)

NET "CLK_50M" LOC = T8 | TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD "sys_clk_pin" 50000 KHz;

##
## reset pushbutton
NET RSTn                  LOC = L3 | IOSTANDARD = "LVCMOS33";
##

########LED Pin define#####################
## LED1
NET led<0>                LOC = P4 | IOSTANDARD = "LVCMOS33";
## LED2
NET led<1>                LOC = N5 | IOSTANDARD = "LVCMOS33";
## LED3
NET led<2>                LOC = P5 | IOSTANDARD = "LVCMOS33";
## LED4
NET led<3>                LOC = M6 | IOSTANDARD = "LVCMOS33";

########KEY Pin define#####################
## KEY1
NET key_in<0>             LOC = C3 | IOSTANDARD = "LVCMOS33";
## KEY2
NET key_in<1>             LOC = D3 | IOSTANDARD = "LVCMOS33";
## KEY3
NET key_in<2>             LOC = E4 | IOSTANDARD = "LVCMOS33";
## KEY4
NET key_in<3>             LOC = E3 | IOSTANDARD = "LVCMOS33";