priority of setup/hold

最新推荐文章于 2025-06-18 01:30:47 发布

转载最新推荐文章于 2025-06-18 01:30:47 发布 · 171 阅读

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原文链接：http://www.cnblogs.com/testset/archive/2013/05/24/3096724.html

本文详细解析了SDC文件中路径约束的优先级规则，包括period、setup/hold、create_clock等关键字的使用及相互之间的优先级关系。讨论了set_input_delay和set_output_delay的特性和如何在FPGA设计中正确应用这些约束，同时解释了不同层级约束的优先级以及特殊情况下set_max_delay和set_min_delay的应用。通过实例说明了在SDC文件中设置路径约束时的注意事项。

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		period	setup/hold	applied to	add
4	create_clock	√	√	node	second assignment will be ignored
	CREATE_GENERATED_CLOCK	√	√	node	ignore the new constraint and issue a warning
	DERIVE_PLL_CLOCKS	√	√	node
	SET_INPUT_DELAY/ SET_OUTPUT_DELAY		√	node(external)	there is another external register connected to the port override the first two lines and a warning would be issued
3	SET_MULTICYCLE_PATH		√	between keepers/clocks
2	SET_MAX_DELAY/SET_MIN_DELAY		√	between keepers/clocks
1	SET_CLOCK_GROUPS		√	clock
1	SET_FALSE_PATH		√	between keepers/clocks

the priority of Set_input_delay and set_output_delay

according to the previous priority of period, the create_clock, create_generated_clock will ignore the second one

set_input_delay and set_output_delay describe a circuit outside of the FPGA.

set_input_delay and set_output_delay assignments will overwrite any previous input or output constraints. and a warning would be issued.

-add_delay option means there is another external register connected to the port.

Priority between Equal Constraints by different levels

This is when a path has two different multicycles assignments applied to it, or two different set_max_delay assignments.

These could be from two different .sdc files, or two different levels of assignments.

By levels,one directly on the path and one between the clocks.

The priority is quite simple, it is whatever constraint is read in last.

One final note is the special case when set_max_delay and set_min_delay are applied to an I/O port that has no set_input_delay or set_output_delay assignment. As discussed, this special case will implicitly add a set_input_delay or set_output_delay constraint to the I/O with 0ns external delay and a clock called “n/a” behind the scenes. This only occurs if the user does not have a set_input_delay or set_output_delay constraint anywhere in their .sdc files. If they do, those constraints take priority over these implicit constraints.

转载于:https://www.cnblogs.com/testset/archive/2013/05/24/3096724.html