PLL失锁的问题

最新推荐文章于 2024-11-11 15:58:42 发布

初仔仔

最新推荐文章于 2024-11-11 15:58:42 发布

阅读量3.6k

点赞数 1

CC 4.0 BY-SA版权

文章标签：嵌入式 javascript ViewUI

原文链接：http://www.cnblogs.com/constanto/p/8568903.html

PLL（相位锁定环）可能因输入时钟抖动过大、同步开关噪声、电源噪声、输入时钟异常、复位操作、重配置、温度过低、频率超出锁区或PFD禁用等原因失去锁相。解决方法包括调整PLL带宽、检查电源稳定性、避免输入异常等。

摘要生成于 C知道，由 DeepSeek-R1 满血版支持，前往体验 >

Possible Causes for PLL Loss of Lock

A phase-locked loop (PLL) can lose lock for a number of reasons. The following are some common causes for the PLL to loselock. If the explanation of these causes do not resolve your issue, submit aservice request to mySupport, Altera's technical online support system.

1.Jitter on PLL input clock is out ofspecification

Excessive jitter on the input clock cancause the PLL to lose lock. For PLL input jitter specification, refer to the DCand Switching Characteristics chapter in the device family handbook.

Since the PLL acts as a low-pass filter,you can use it to filter input jitter as well. The programmable bandwidth feature allows you to control the low-pass response characteristics. To filter higher frequency jitter, use a low bandwidth setting. To track jitter, use ahigh bandwidth setting. Refer to the PLL chapter in the device family handbook to check whether the PLL in that device supports the programmable bandwidth feature.

To check whether jitter is a problem,compare your input clock’s jitter characteristics (in the frequency domain)with the PLL’s bandwidth (reported in the Quartus® II PLL Summary Report file).If your jitter frequency is within the bandwidth or falls near the edge of the bandwidth, it could be coupling through or being slightly amplified (due tojitter peaking).

2.Simultaneous switching noise (SSN)

Excessive switching noise on the clock inputs o