Modelsim仿真出错

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modelsim 仿真出错

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错误编号：ERROR 138003 and ERROR 140001

在Quartus prime 对工程文件修改后，未关闭modelsim窗口，直接运行do project_name_run_msim_rtl_verilog.do会出现如下错误信息。

错误信息：Error (138003): Can’t write incremental compilation assignments. Quartus Prime Settings File C:/Users/Administrator/Desktop/test_trans/low_trans_test_1220/low_trans_test/low_trans_test.qsf is unwritable.

Error (140001): Can’t write LogicLock assignments. The Quartus Prime Settings File C:/Users/Administrator/Desktop/test_trans/low_trans_test_1220/low_trans_test/low_trans_test.qsf is unwritable.

解决方案 关闭modelsim，重新运行tools-> Run Simulation Tool->Rtl Simulation。