# Rules of makefile:
# target ... : prerequisites ...
# (\t)command
# ...
# if there is no foo.make or any files whose name end up with .mk, the make will exit with error
include foo.make *.mk
# It won't exit with error code if perhapsError.mk has error, when we use '-' before include
-include perhapsError.mk
#main: main.o
# g++ -o main main.o
#main.o : main.cpp json.hpp
# g++ -c main.cpp
# a kind of var, like macro definition, CXX will be just replace with g++ when making.
# Must assign var a initial value
CXX = g++
CXXFLAGS = -Wall
# another kind of a var, we can add values to it with "+="
BUILD_DIR := ./build
# We use var by using $(var)
OBJ_DIR := $(BUILD_DIR)/obj
TARGET := main2
SOURCE := main.cpp
SOURCE += json.hpp main2.cpp # If we don't write json.hpp here, it still make correct. why?
#OBJ := main.o main2.o
OBJ := $(SOURCE:%.cpp=$(OBJ_DIR)/%.o)
# $@ means the object, here is $(BUILD)/$(TARGET), also known as ./build/main2
# $^ means all the prerequistites
# $(@D) means the directory part of the object. which is ./build of ./build/main2
# $(@F) means the file part of the object.
# So, the following equals:
# @mkdir -p ./build
# main2: main.o
# g++ -o main2 main.o main2.o
$(BUILD_DIR)/$(TARGET): $(OBJ)
@mkdir -p $(@D)
$(CXX) $(CXXFLAGS) -o $@ $^
# Pay Attention!!! windows powershell can't use "mkdir -p". we should use git bash on windows
# $< means the first prerequisties
# % means every
# So, the following equals:
# @mkdir -p ./build/obj
# ./build/obj/main.o : main.cpp
# g++ -Wall -o ./build/obj/main.o -c main.cpp
# ./build/obj/main2.o : main2.cpp
# g++ -Wall -o ./build/obj/main.o -c main.cpp
$(OBJ_DIR)/%.o: %.cpp
@mkdir -p $(@D)
$(CXX) $(CXXFLAGS) -o $@ -c $<
# .PHONY: aaa bbb ccc ddd
# .PHONY defined a group of fake target. Which will always be done when called.
.PHONY: clean
# It is a certainly good idea to put clean at the end of the Makefile.
clean:
-@rm -rvf $(BUILD_DIR)