Verilog实现数字频率计

搞了块fpga随便玩玩

所用器材：fpga开发板（内部时钟频率位27MHz），四位共阴极数码管。

实现功能：0Hz-9999Hz频率测量（这种做法，有六位数码管测量范围也可以扩容到1MHz）

计数方法：测定1hz时钟下输入信号的上升沿次数

各个模块：

1.控制模块

module control(clk_1Hz, rst_n, count_en, latch_en, clear);
input clk_1Hz, rst_n;
output count_en, latch_en, clear;
reg count_en, latch_en, clear;
reg [1:0] state;
always@(posedge clk_1Hz or negedge rst_n)
if(!rst_n)
begin
state <=2'd0;count_en<=1'b0;
latch_en<= 1'b0;clear<=1'b0;
end
else
begin
case(state)
2'd0:
begin
count_en<=1'b1;latch_en<=1'b0;
clear<=1'b0;state<=2'd1;
end
2'd1:
begin
count_en<=1'b0;latch_en<=1'b1;
clear<=1'b0; state<=2'd2;
end
2'd2:
begin
count_en<= 1'b0;latch_en<=1'b0;
clear<=1'b1; state<=2'd0;
end
default