m序列,其中本源函数为x15+x14+1
单bit输出:
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2024/10/17 11:56:43
// Design Name:
// Module Name: LFSR15_C001
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module LFSR15_C001(
input clk,
input reset,
output reg [14:0] LFSR = 15'b00000_000000_11111,
output reg pn_out,
output reg [7:0]bit_counter
);
always @(posedge clk)
begin
if (reset)
begin
LFSR = 15'b00000_000000_11111;
bit_counter<=0;
pn_out<=0;
end
else
begin
LFSR[0] <= LFSR[13] ^ LFSR[14];
LFSR[14:1] <= LFSR[13:0];
pn_out<=LFSR[14];
end
if(bit_counter<15)
bit_counter<=bit_counter+1;
else
bit_counter<=0;
end
endmodule
其中testbench代码为:
`timescale 1ns / 1ps
module tb_LFSR15_C001;
// Inputs
reg clk;
reg reset;
// Outputs
wire [14:0] LFSR;
wire pn_out;
wire [7:0] bit_counter;
// Instantiate the LFSR module
LFSR15_C001 uut (
.clk(clk),
.reset(reset),
.LFSR(LFSR),
.pn_out(pn_out),
.bit_counter(bit_counter)
);
// Clock generation (50 MHz clock -> 10ns period)
initial begin
clk = 0;
forever #5 clk = ~clk; // 每5ns翻转一次时钟,得到10ns的时钟周期
end
// Initial block for test sequence
initial begin
// Display the header
$display("Time\t\tReset\tLFSR\t\tpn_out\tbit_counter");
// Apply reset signal
reset = 1;
#15 reset = 0; // 15ns后取消复位
// Monitor outputs
$monitor("%0dns\t%b\t%b\t%b\t%d", $time, reset, LFSR, pn_out, bit_counter);
// Run the simulation for 200 ns
#200 $finish;
end
endmodule