任意整数分频时钟的建立

1.该程序使用Verilog语言，用状态机实现任意整数分频的时钟；
2.偶数分频和奇数分频都能实现；
2.在运算中把除法和取余逻辑上比较好理解的运算符，改变成右移位和减法实现，可以大量节省FPGA资源；

module div(
input	wire				clk,
input	wire				rst,
input	wire	[31:0]	a,     //任意分频倍数

output	wire			clk_a
);
reg		clk1;
reg		clk2;

wire		[31:0]	T_H;
wire		[31:0]	T_L;
assign	T_H = a >> 1 ;
assign	T_L = a-(a>>1);
reg	[31:0]	cnt;

localparam   CLK_H = 0;
localparam   CLK_L = 1;
reg	[1:0]	cstate;

always@(posedge clk or posedge rst)
	if(rst)
		begin
			clk1<=0;
			cnt<=0;
			cstate <= CLK_H;
		end	
	else
		case(cstate)
			CLK_H		:		begin
									clk1<=1;
									if(cnt == T_H - 1)
										begin	cstate <= CLK_L;	cnt<=0;	end
									else
										begin	cstate <= CLK_H;	cnt<=cnt+1;	end
								end
								
			CLK_L		:		begin
									clk1<=0;
									if(cnt == T_L - 1)
										begin	cstate <= CLK_H;	cnt<=0;	end
									else
										begin	cstate <= CLK_L;	cnt<=cnt+1;	end
								end
								
			default	:		;
		endcase

		

always@(negedge clk or posedge rst)
	if(rst)
		clk2 <= 0;
	else
		case(cstate)
			CLK_H		:		clk2<=1;
								
			CLK_L		:		clk2<=0;
			
			default	:		;
		endcase

assign	clk_a = (a-(a>>1)-(a>>1)) ? (clk1 || clk2) : clk1;
	
endmodule