SPI - Serial Peripheral Interface

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Preface

With this article, the possibilities of serial communication with peripheral devices via SPI (Serial Peripheral Interface) will be discussed. More and more serial bus systems are preferred instead of a parallel bus, because of the simpler wiring. As the efficiency of serial buses increases, the speed advantage of the parallel data transmission gets less important. The clock frequencies of SPI devices can go up to some Megahertz and more. There are a lot of application where a serial transmission is perfectly sufficient. The usage of SPI is not limited to the measuring area, also in the audio field this type of transmission is used.

The SPI (this name was created by Motorola) is also known as Microwire, trade mark of National Semiconductor. Both have the same functionality. There are also the extensions QSPI (Queued Serial Peripheral Interface) and MicrowirePLUS.

The popularity of other serial bus systems like I²C, CAN bus or USB shows, that serial buses get used more and more.

Below is a list of SPI devices. However this list neither claims to be complete nor is the availablability of the listed components guaranteed. In addition there is a list ofmanufacturers with the type of SPI components they produce.

Martin Schwerdtfeger, 06/2000

The Principle

The Serial Peripheral Interface is used primarily for a synchronous serial communication of host processor and peripherals. However, a connection of two processors via SPI is just as well possible and is described at the end of the chapter.

In the standard configuration for a slave device (see illustration 1), two control and two data lines are used. The data output SDO serves on the one hand the reading back of data, offers however also the possibility to cascade several devices. The data output of the preceding device then forms the data input for the next IC.

Illustration 1: SPI slave

There is a MASTER and a SLAVE mode. The MASTER device provides the clock signal and determines the state of the chip select lines, i.e. it activates the SLAVE it wants to communicate with. CS and SCKL are therefore outputs.

The SLAVE device receives the clock and chip select from the MASTER, CS and SCKL are therefore inputs.

This means there is one master, while the number of slaves is only limited by the number of chip selects.

A SPI device can be a simple shift register up to an independent subsystem. The basic principle of a shift register is always present. Command codes as well as data values are serially transferred, pumped into a shift register and are then internally available for parallel processing. Here we already see an important point, that must be considered in the philosophy of SPI bus systems: The length of the shift registers is not fixed, but can differ from device to device. Normally the shift registers are 8Bit or integral multiples of it. Of course there also exist shift registers with an odd number of bits. For example two cascaded 9Bit EEPROMs can store 18Bit data.

If a SPI device is not selected, its data output goes into a high-impedance state (hi-Z), so that it does not interfere with the currently activated devices. When cascading several SPI devices, they are treated as one slave and therefore connected to the same chip select.

Thus there are two meaningful types of connection of master and slave devices. illustration 2 shows the type of connection for cascading several devices.

Illustration 2: Cascading several SPI devices

In illustration 2 the cascaded devices are evidently looked at as one larger device and receive therefore the same chip select. The data output of the preceding device is tied to the data input of the next, thus forming a wider shift register.

If independent slaves are to be connected to a master an other bus structure has to be chosen, as shown in illustration 3. Here, the clock and the SDI data lines are brought to each slave. Also the SDO data lines are tied together and led back to the master. Only the chip selects are separately brought to each SPI device.

Illustration 3: Master with independent slaves

Last not least both types may be combined.

It is also possible to connect two micro controllers via SPI. For such a network, two protocol variants are possible. In the first, there is only one master and several slaves and in the second, each micro controller can take the role of the master. For the selection of slaves again two versions would be possible but only one variant is supported by hardware. The hardware supported variant is with the chip selects, while in the other the selection of the slaves is done by means of an ID packed into the frames. The assignment of the IDs is done by software. Only the selected slave drives its output, all other slaves are in high-impedancd state. The output remains active as long as the slave is selected by its address.

The first variant, named single-master protocol, resembles the normal master-slave communication. The micro controller configured as a slave behaves like a normal peripheral device.

The second possibility works with several masters and is therefore named multi-master protocol. Each micro processor has the possibility to take the roll of the master and to address another micro processor. One controller must permanently provide a clock signal. The MC68HC11 provides a harware error recognition, useful in multiple-master systems. There are two SPI system errors. The first occurs if several SPI devices want to become master at the same time. The other is a collision error that occurs for example when SPI devices work with with different polarities. More details can be found in the MC68HC11 manual.

Data and Control Lines of the SPI

The SPI requires two control lines (CS and SCLK) and two data lines (SDI and SDO). Motorola names these lines MOSI (Master-Out-Slave-In) and MISO (Master-In-Slave-Out). The chip select line is named SS (Slave-Select).

With CS (Chip-Select) the corresponding peripheral device is selected. This pin is mostly active-low. In the unselected state the SDO lines are hi-Z and therefore inactive. The master decides with which peripheral device it wants to communicate. The clock line SCLK is brought to the device whether it is selected or not. The clock serves as synchronization of the data communication.

The majority of SPI devices provide these four lines. Sometimes it happens that SDI and SDO are multiplexed, for example in the temperature sensor LM74 from National Semiconductor, or that one of these lines is missing. A peripheral device which must or can not be configured, requires no input line, only a data output. As soon as it gets selected it starts sending data. In some ADCs therefore the SDI line is missing (e.g. MCCP3001 from Microchip).

There are also devices that have no data output. For example LCD controllers (e.g. COP472-3 from National Semiconductor), which can be configured, but cannot send data or status messages.

SPI Configuration

Because there is no official specification, what exactly SPI is and what not, it is necessary to consult the data sheets of the components one wants to use. Important are the permitted clock frequencies and the type of valid transitions.

There are no general rules for transitions where data shouls be latched. Although not specified by Motorola, in practice four modes are used. These four modes are the combinations of CPOL and CPHA. In table 1, the four modes are listed.

SPI-mode	CPOL	CPHA
0 1 2 3	0 0 1 1	0 1 0 1

Table 1: SPI Modes

If the phase of the clock is zero, i.e. CPHA = 0, data is latched at the rising edge of the clock with CPOL = 0, and at the falling edge of the clock with CPOL = 1. If CPHA = 1, the polarities are reversed. CPOL = 0 means falling edge, CPOL = 1 rising edge.

The micro controllers from Motorola allow the polarity and the phase of the clock to be adjusted. A positive polarity results in latchig data at the rising edge of the clock. However data is put on the data line already at the falling edge in order to stabilize. Most peripherals which can only be slaves, work with this configuration. If it should become necessary to use the other polarity, transitions are reversed.

The different Peripheral Types

The question is of course, which peripheral types exist and which can be connected to the host processor. The available types and their characteristics are now discussed. Peripheral types can be subdivided into the following categories:

• Converters (ADC and DAC)
• Memories (EEPROM and FLASH)
• Real Time Clocks (RTC)
• Sensors (temperature, pressure)
• Others (signalmixer, potentiometer, LCD controller, UART, CAN controller, USB controller, amplifier)

In the three categories converters, memories and RTCs, there is a great variety of component. Devices belonging to the last both groups are more rarely.

There are lots of converters with different resolutions, clock frequencies and number of channels to choose from. 8, 10, 12 up to 24Bit with clock frequencies from 30ksps up to 600ksps.

Memory devices are mostly EEPROM variants. There are also a few SPI flash memories. Capacities range from a couple of bits up to 64KBit. Clock frequencies up to 3MHz. Serial EEPROMS SPI are available for different supply voltages (2.7V to 5V) allowing their use in low-voltage applications. The data retention time duration from 10 years to 100 years. The permitted number of write accesses is 1 million cycles for most components. By cascading memory devices any number of bits/word can be obtained.

RTCs are ideally suited for serial communication because only small amounts of data have to be transferred. There is also a great variety of RTCs with supply voltages from 2.0V. In addition to the standard functions of a "normal" clock, some RTCs offer an alarm function, non-volatile RAM etc. Most RTCs come from DALLAS and EPSON.

The group of the sensors is yet weakly represented. Only a temperature and a pressure sensor could be found.

CAN and USB controllers with SPI make it easier to use these protocols on a micro controller and inerfacing a LCD via SPI saves the troublesome parallel wiring.