HDMI720x576P50Hz BT656时序的彩条视频流

720x576P50Hz

`timescale 1ns / 1ps
//
// Company: 
// Engineer: Q
// 
// Create Date: 2020/08/28 10:29:00
// Design Name: 
// Module Name: gen720x576p50Hz_BT656
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: clock 27MHz
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module gen720x576p50Hz_BT656(
input wire clk,
input wire i_rst_b,

output reg       o_v_sync  ,
output reg       o_h_sync  ,
output reg       o_de_sync ,
output reg [7:0] ov_y_data ,
output reg [7:0] ov_c_data

);

localparam H_SYNC_LOW  = 64;
localparam H_SYNC_HIGH = 864;
localparam TOTAL_LINE  = 625;

  
reg h_sync_p;
reg [9:0]h_sync_cnt;
always @(posedge clk)
begin
if(!i_rst_b)
begin
  h_sync_p <= 1;
  h_sync_cnt <= 0;
end
else
begin
  if(h_sync_cnt==H_SYNC_LOW-1)
  begin
    h_sync_p <= 1;
    h_sync_cnt <= h_sync_cnt + 1;
  end
  else if(h_sync_cnt==H_SYNC_HIGH-1)
  begin
    h_sync_p <= 0;
    h_sync_cnt <= 0;
  end
  else
  begin
    h_sync_cnt <= h_sync_cnt + 1;
  end
end
end


reg h_sync;
always @(posedge clk)
begin
h_sync <= h_sync_p;
end

wire h_sync_falling = (h_sync != h_sync_p) && (h_sync ==1) ;

reg [9:0] h_line_cnt;
always @(posedge clk)
begin
if(!i_rst_b)
begin
  h_line_cnt <= 0;
end
else
begin
  if(h_sync_falling)
  begin
    if(h_line_cnt==TOTAL_LINE)
    begin
      h_line_cnt <= 1;
    end
    else
    begin
      h_line_cnt <= h_line_cnt + 1;
    end
  end
  else
  begin
    h_line_cnt <= h_line_cnt;
  end
end
end


wire v_sync;
assign v_sync = ~(h_line_cnt < 6);


reg de_sync_p ;
always @(posedge clk)
begin
    if(!i_rst_b)
    begin
      de_sync_p <= 0;
    end
    else
    begin
      de_sync_p <= h_sync_cnt > 131 && (h_sync_cnt < 852);
    end
end

wire de_sync;
assign de_sync = de_sync_p & ((h_line_cnt > 44)&&(h_line_cnt < 621));


reg Cbcr=0;
always @(posedge clk)
begin
    if(!i_rst_b)
    begin
      Cbcr <= 0;
    end
    else
    begin
      if(de_sync)Cbcr <= ~Cbcr;
      else Cbcr <= 0;
    end
end

localparam DEVIDE_1 = 188;
localparam DEVIDE_2 = 332;
localparam DEVIDE_3 = 476;

always @(posedge clk)
begin
o_v_sync  <= v_sync ;
o_h_sync  <= h_sync ;
o_de_sync <= de_sync;
    if(h_line_cnt<DEVIDE_1)
    begin
        ov_y_data <= de_sync ? 8'h80:8'h10; // gray
        ov_c_data <= de_sync ? 8'h80:8'h80;
    end
    else if(h_line_cnt<DEVIDE_2)
    begin
        ov_y_data <= de_sync ?        8'h4c:      8'h10; // red
        ov_c_data <= de_sync ? Cbcr ? 8'hff:8'h54:8'h80;
    end
    else if(h_line_cnt<DEVIDE_3)
    begin
        ov_y_data <= de_sync ?        8'h95      :8'h10; // green
        ov_c_data <= de_sync ? Cbcr ? 8'h15:8'h2b:8'h80;
    end
    else
    begin
        ov_y_data <= de_sync ?        8'h1d      :8'h10; // blue
        ov_c_data <= de_sync ? Cbcr ? 8'h6b:8'hff:8'h80;
    end
end

endmodule