Modelsim比较器仿真

代码截图：

代码： 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity zy7 is
  port(a,b:in std_logic_vector(3 downto 0);
      y,y1,y2:out std_logic);
    end entity zy7;
architecture jgt of zy7 is
  begin
    process(a,b)
      begin
        if(a>b) then
          y<='1';y1<='0';y2<='0';
        elsif(a=b) then
          y<='0';y1<='1';y2<='0';
        else
          y<='0';y1<='0';y2<='