VLSI/SoC设计综合实验（Ⅲ-后期）

VLSI/SoC设计综合实验（Ⅲ-后期）

作者： Saint
掘金：https://juejin.im/user/5aa1f89b6fb9a028bb18966a
微博：https://weibo.com/5458277467/profile?topnav=1&wvr=6&is_all=1
GitHub：github.com/saint-000

源码：

--失分鸣响电路
library ieee;
use ieee.std_logic_1164.all;
entity sound is
port(	clk:in std_logic;
	sig:in std_logic;
	en:in std_logic;
	sout:out std_logic);   
end sound;
architecture ful of sound is
begin
sout<=clk and (not sig) and en;
end;  

--兵乓球游戏总控制模块
library ieee;
use ieee.std_logic_1164.all;
entity ballctrl is
	port(	clr:in std_logic;
		bain:in std_logic;
		bbin:in std_logic;
		serclka:in std_logic;
		serclkb:in std_logic;
		clk:in std_logic;
		bdout:out std_logic;
		serve:out std_logic;
		serclk:out std_logic;
		ballclr:out std_logic;
		ballen:out std_logic);
end ballctrl;
architecture ful of ballctrl is
	signal bd:std_logic;
	signal ser:std_logic;
	--signal jq:std_logic;
begin
	bd<=bain or bbin;
	ser<=serclka or serclkb;
	serclk<=ser;	  --球拍正确接球信号
	bdout<=bd;	  --球拍接球脉冲
	--jq<=bbin and serclkb;
	process(clk,clr,bd)
	begin
		
		if(clr='1')then	--系统复位
			serve<='1';		--系统处于发球状态
			ballclr<='1';   --球灯清零
		else --系统正常
			
			if(bd='1')then	--球拍发球或接球时
				ballclr<='1';	--球灯清零
				
				if(ser='1')then	--球拍正确发球或正确接球
					ballen<='1';	--球灯使能
					serve<='0';		--系统处于接球状态
					
				else ballen<='0';
					serve<='1';
				end if;
			else ballclr<='0';
			end if;
		end if;
	end process;
end;


--兵乓球灯模块
library ieee;
   use ieee.std_logic_1164.all;
   use ieee.std_logic_unsigned.all;
entity ball is
port(
	clk:in std_logic;
	clr:in std_logic;
	way: in std_logic;
	en: in std_logic;
	ballout: out std_logic_vector(7 downto 0));
end ball;
architecture ful of ball is
signal lamp: std_logic_vector(9 downto 0);
begin
process(clk,clr,en)
begin
	if(clr='1')then lamp<="0111111110";
	elsif en='0' then
	elsif (clk'event and clk ='1')then
	if(way ='1')then
		lamp(9 downto 1)<=lamp(8 downto 0);	 --o有效
		lamp(0)<='1';
	else lamp(8 downto 0)<=lamp(9 downto 1);
		lamp(9)<='1';
end if;
end if;
ballout<=lamp(8 downto 1);
end process;
end;





--兵乓拍模块
library ieee;
use ieee.std_logic_1164.all;
entity board is
port(
	ball: in std_logic;
	net: in std_logic;
	bclk: in std_logic;
	serve: in std_logic;
	couclk: out std_logic;
	serclk: out std_logic);
	end board;
architecture ful of board is
begin
process(bclk,net)
begin
	if(net='0')then
		serclk<='0';
		couclk<='0';
	elsif(bclk'event and bclk='1')then
	if(serve ='1')then serclk<='1';
	else
	if(ball='0')then
	serclk<='1';
	else serclk<='0';
	couclk<='1';
end if;
end if;
end if;
end