POJ - 1251 最小生成树


The Head Elder of the tropical island of Lagrishan has a problem. A burst of foreign aid money was spent on extra roads between villages some years ago. But the jungle overtakes roads relentlessly, so the large road network is too expensive to maintain. The Council of Elders must choose to stop maintaining some roads. The map above on the left shows all the roads in use now and the cost in aacms per month to maintain them. Of course there needs to be some way to get between all the villages on maintained roads, even if the route is not as short as before. The Chief Elder would like to tell the Council of Elders what would be the smallest amount they could spend in aacms per month to maintain roads that would connect all the villages. The villages are labeled A through I in the maps above. The map on the right shows the roads that could be maintained most cheaply, for 216 aacms per month. Your task is to write a program that will solve such problems.

Input
The input consists of one to 100 data sets, followed by a final line containing only 0. Each data set starts with a line containing only a number n, which is the number of villages, 1 < n < 27, and the villages are labeled with the first n letters of the alphabet, capitalized. Each data set is completed with n-1 lines that start with village labels in alphabetical order. There is no line for the last village. Each line for a village starts with the village label followed by a number, k, of roads from this village to villages with labels later in the alphabet. If k is greater than 0, the line continues with data for each of the k roads. The data for each road is the village label for the other end of the road followed by the monthly maintenance cost in aacms for the road. Maintenance costs will be positive integers less than 100. All data fields in the row are separated by single blanks. The road network will always allow travel between all the villages. The network will never have more than 75 roads. No village will have more than 15 roads going to other villages (before or after in the alphabet). In the sample input below, the first data set goes with the map above.
Output
The output is one integer per line for each data set: the minimum cost in aacms per month to maintain a road system that connect all the villages. Caution: A brute force solution that examines every possible set of roads will not finish within the one minute time limit.
Sample Input
9
A 2 B 12 I 25
B 3 C 10 H 40 I 8
C 2 D 18 G 55
D 1 E 44
E 2 F 60 G 38
F 0
G 1 H 35
H 1 I 35
3
A 2 B 10 C 40
B 1 C 20
0
Sample Output
216

30

 题意:N个小岛里要修桥,就是每个岛之间要直接或间接连接起来,就是一个简单的最小生成树的题,直接用Kruskal就可以。

代码如下:

#include <iostream>
#include <cstdio>
#include <algorithm>
using namespace std;
int fa[27];
struct edge // 储存两个点之间的距离
{
    int u, v, w;
}map[80];
void init()
{
    for(int i = 0; i < 27; i++)
        fa[i] = i;
}
bool cmp(edge a, edge b)
{
    return a.w < b.w;
}
int find(int x)
{
    if(x == fa[x]) return x;
    return fa[x] = find(fa[x]);
}

int main()
{
    int n;
    while(cin >> n && n)
    {
        init();
        int k = 0;
        for(int i = 0; i < n - 1; i++)
        {
            char str[3];
            int m;
            cin >> str >> m;
            for(int j = 0; j < m; j++, k++)  // 输入数据, 注意细节
            {
                char str2[3];
                int t;
                cin >> str2 >> t;
                map[k].u = (str[0] - 'A');
                map[k].v = (str2[0] - 'A');
                map[k].w = t;
            }
        }
        sort(map, map + k, cmp); // 排序,找最短
        int ans = 0;
        for(int i = 0; i < k; i++) 
        {
            int x = find(map[i].u);
            int y = find(map[i].v);
            if(x != y)
            {
                ans += map[i].w;
                fa[x] = y;
            }
        }
        cout << ans << endl;
    }
    return 0;
}


在电子设计自动化(EDA)领域,Verilog HDL 是一种重要的硬件描述语言,广泛应用于数字系统的设计,尤其是在嵌入式系统、FPGA 设计以及数字电路教学中。本文将探讨如何利用 Verilog HDL 实现一个 16×16 点阵字符显示功能。16×16 点阵显示器由 16 行和 16 列的像素组成,共需 256 个二进制位来控制每个像素的亮灭,常用于简单字符或图形显示。 要实现这一功能,首先需要掌握基本的逻辑门(如与门、或门、非门、与非门、或非门等)和组合逻辑电路,以及寄存器和计数器等时序逻辑电路。设计的核心是构建一个模块,该模块接收字符输入(如 ASCII 码),将其转换为 16×16 的二进制位流,进而驱动点阵的 LED 灯。具体而言,该模块包含以下部分:一是输入接口,通常为 8 位的 ASCII 码输入,用于指定要显示的字符;二是内部存储,用于存储字符对应的 16×16 点阵数据,可采用寄存器或分布式 RAM 实现;三是行列驱动逻辑,将点阵数据转换为驱动 LED 矩阵的信号,包含 16 个行输出线和 16 个列使能信号,按特定顺序选通点亮对应 LED;四是时序控制,通过计数器逐行扫描,按顺序控制每行点亮;五是复用逻辑(可选),若点阵支持多颜色或亮度等级,则需额外逻辑控制像素状态。 设计过程中,需用 Verilog 代码描述上述逻辑,并借助仿真工具验证功能,确保能正确将输入字符转换为点阵显示。之后将设计综合到目标 FPGA 架构,通过配置 FPGA 实现硬件功能。实际项目中,“led_lattice”文件可能包含 Verilog 源代码、测试平台文件、配置文件及仿真结果。其中,测试平台用于模拟输入、检查输出,验证设计正确性。掌握 Verilog HDL 实现 16×16 点阵字符显示,涉及硬件描述语言基础、数字逻辑设计、字符编码和 FPGA 编程等多方面知识,是学习
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