FPGA axi-quad-spi IP核寄存器说明

最新推荐文章于 2024-06-09 08:34:02 发布

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最新推荐文章于 2024-06-09 08:34:02 发布 · 6.3k 阅读

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40：(SRR) IP核复位寄存器
写入0000_000A复位

60：(SPICR) SPI控制寄存器
Default Value：0x180

[31:10]	Reserved

[9:9]	(LSB First)

		0 = MSB first transfer format.	1 = LSB first transfer format.

[8:8]	(Master Transaction Inhibit)

		0 = Master transactions enabled.	1 = Master transactions disabled.

[7:7]	(Manual Slave Select Assertion Enable)

		0 = Slave select output asserted by master core logic.
		1 = Slave select output follows data in slave select register.

[6:6]	(RX FIFO Reset)

		0 = Receive FIFO normal operation.		1 = Reset receive FIFO pointer.

[5:5]	(TX FIFO Reset)

		0 = Transmit FIFO normal operation.	1 = Reset transmit FIFO pointer.

[4:4]	(CPHA)	Clock phase:(时钟相位)

		时钟相位是指数据的采样的时刻，决定MOSI或MISO数据线上的信号将会在SCK时钟线的"奇数边沿"被采样或者数据线在SCK的"偶数边沿"采样。

[3:3]	(CPOL)	Clock polarity:(时钟极性)

		时钟极性是指SPI通讯设备处于空闲状态时，SCK信号线的电平信号(即SPI通讯开始前、 CS线为高电平时SCK的状态)。

		0 = Active-High clock; SCK idles Low.	1 = Active-Low clock; SCK idles High.

[2:2]	(Master)	Master (SPI master mode