Quartus实现数字钟

利用Quartus实现一个简易的数字钟，功能包括调整时分秒，整点报时，并且支持不同频率调整。

module DigitalClock(seg0,seg1,seg2,seg3,seg4,seg5,seg6,seg7,D0,D1,D2,D3,D4,D5,Alarm,CP,CR,CE,Adj_Min,Adj_Hour,dis,changan);
		input CP,CR,CE,Adj_Min,Adj_Hour,changan;
		output [6:0]seg0,seg1,seg2,seg3,seg4,seg5,seg6,seg7;
		output [3:0]D0,D1,D2,D3,D4,D5;
		output Alarm;
		output [7:0]dis;
		wire Alarm;
		wire [7:0] Hour,Min,Sec;
		wire [6:0]seg0,seg1,seg2,seg3,seg4,seg5,seg6,seg7;
		wire [3:0]D0,D1,D2,D3,D4,D5;
		supply1 Vdd;//1
		wire MinL_CE,MinH_CE,Hour_CE;
		reg [7:0]dis;
		
		clk_1hz t(CP, CE, CLK);//分频模块的实现,仿真需要注释,同时将cp改为clk
		clk_10hz t2(CP,CE,CLK10);
		counter10 U1(Sec[3:0],CLK,CE,CR);//
		counter6 U2(Sec[7:4],CLK,(Sec[3:0]==4'h9),CR);//
		assign MinL_CE= Adj_Min?Vdd:((Sec == 8'h59) || (~changan));//未到59秒也可调整分钟
		assign MinH_CE=((Adj_Min) && (Min[3:0]==4'h9)) || ((Min[3:0]==4'h9) && (Sec==8'h59)) ||((~changan) && (Min[3:0]==4'h9));
		counter10 U3(Min[3:0],(~changan?CLK10:CLK),MinL_CE,CR);//(changan?CLK:CLK10)
		counter6 U4(Min[7:4],(~changan?CLK10:CLK),MinH_CE,CR);//
		assign Hour_CE = Adj_Hour?Vdd : ( (Min==8'h59) && (Sec==8'h59) );
		counter24 U5(Hour[7:4],Hour[3:0],CLK,Hour_CE,CR);//
		dingshi ds(Alarm,Min,Sec,CP);
		Transform T1(Sec[3:0],D0);
		Transform T2(Sec[7:4],D1);
		Transform T3(Min[3:0],D2);
		Transform T4(Min[7:4],D3);
		Transform T5(Hour[3:0],D4);
		Transform T6(Hour[7:4],D5);
		seg7_decoder S0(D0,seg0);
		seg7_decoder S1(D1,seg1);
		seg7_decoder S2(D2,seg2);
		seg7_decoder S3(D3,seg3);
		seg7_decoder S4(D4,seg4);
		seg7_decoder S5(D5,seg5);
		seg7_decoder S7(4'b1111,seg7);
		seg7_decoder S6(4'b1111,seg6);
//		seg7_decoder S0(Sec[3:0],seg0);
//		seg7_decoder S1(Sec[7:4],seg1);
//		seg7_decoder S2(Min[3:0],seg2);
//		seg7_decoder S3(Min[7:4],seg3);
//		seg7_decoder S4(Hour[3:0],seg4);
//		seg7_decoder S5(Hour[7:4],seg5);
		always@(CE)
			if(~CE)
				begin
					dis <=8'hFF;
				end
endmodule

//(2)计数器
//
//十进制
module counter10(Q,CP,CE,CR);
		input CP,CE,CR;
		output [3:0] Q;
		reg  [3:0]Q;
		always@(posedge CP,negedge CR)
		begin
			if(~CR)Q<=4'b0000;
			else if(CE)
				begin
					if(Q>=4'b1001)
						Q<=4'b0000;
					else
						Q<=Q+1'b1;
				end
			else 
				Q<=Q;
		end
endmodule
//六进制
module counter6(Q,CP,CE,CR);
		input CP,CE,CR;
		output [3:0] Q;
		reg  [3:0]Q;
		always@(posedge CP,negedge CR)
		begin
			if(~CR)Q<=4'b0000;
			else if(CE)
				begin
					if(Q>=4'b0101)
						Q<=4'b0000;
					else
						Q<=Q+1'b1;
				end
			else 
				Q<=Q;
		end
endmodule
//二十四进制
module counter24(CntH,CntL,CP,CE,CR);
		input CP,CE,CR;
		output [3:0]CntH,CntL;
		reg [3:0]CntH,CntL;
		always @(posedge CP,negedge CR)
		begin
			if(~CR)
				{CntH,CntL}<=8'h00;
			else if(~CE)
				{CntH,CntL}<={CntH,CntL};
			else if((CntH>2)||(CntL>9)||((CntH==2)&&(CntL>=3)))
				{CntH,CntL}<=8'h00;
			else if((CntH==2)&&(CntL<3))
				begin CntH<=CntH; CntL<=CntL+1'b1;end
			else if(CntL==9)
				begin CntH<=CntH+1'b1; CntL<=4'b0000;end
			else
				begin CntH<=CntH; CntL<=CntL+1'b1;end
		end
endmodule
//分频
module clk_1hz(CLK, EN, clk_1Hz);
    input CLK, EN;
    output clk_1Hz;
    wire clk_1MHz, clk_100KHz, clk_10KHz, clk_1KHz, clk_100Hz, clk_10Hz;
     divide_by_50 d6 (clk_1MHz, CLK, EN);
     divide_by_10 d5 (clk_100KHz, clk_1MHz, EN);
     divide_by_10 d4 (clk_10KHz, clk_100KHz, EN);
     divide_by_10 d3 (clk_1KHz, clk_10KHz, EN);
     divide_by_10 d2 (clk_100Hz, clk_1KHz, EN);
     divide_by_10 d1 (clk_10Hz, clk_100Hz, EN);
     divide_by_10 d0 (clk_1Hz, clk_10Hz, EN);
endmodule

module clk_10hz(CLK,EN,clk_10Hz);
	input CLK, EN;
	output clk_10Hz;
	wire clk_1MHz, clk_100KHz, clk_10KHz, clk_1KHz, clk_100Hz, clk_10Hz;
     divide_by_50 d6 (clk_1MHz, CLK, EN);
     divide_by_10 d5 (clk_100KHz, clk_1MHz, EN);
     divide_by_10 d4 (clk_10KHz, clk_100KHz, EN);
     divide_by_10 d3 (clk_1KHz, clk_10KHz, EN);
     divide_by_10 d2 (clk_100Hz, clk_1KHz, EN);
     divide_by_10 d1 (clk_10Hz, clk_100Hz, EN);
endmodule
 
module divide_by_10 (Q, CLK, EN);
      input CLK, EN;
      output Q;
      reg Q;
      reg [2:0] count;
      always @(posedge CLK or negedge EN)
         begin 
             if (~EN)
                 begin
                     Q <= 1'b0;
                     count <= 3'b000;
                 end
             else if (count < 4)
                 begin
                     count <= count + 1'b1;
                 end
             else
                 begin
                     count <= 3'b000;
                     Q <= ~Q;
                 end
         end
endmodule
 
 module divide_by_50 (Q, CLK, EN);
      input CLK, EN;
      output Q;
      reg Q;
      reg [4:0] count;
      
     always @(posedge CLK or negedge EN)
         begin
             if (~EN)
                 begin
                     Q <= 1'b0;
                     count <= 5'b00000;
                 end
             else if (count < 24)
                 begin
                     count <= count + 1'b1;
                 end
             else
                 begin
                     count <= 5'b00000;
                     Q <= ~Q;
                 end
         end
endmodule


//8421
module Transform(in,out);
		input [3:0]in;
		output [3:0]out;
		reg [3:0]out;
		
		always @(in)
				case(in)
					4'd0: out = 4'b0000;
					4'd1: out = 4'b0001;
					4'd2: out = 4'b0010;
					4'd3: out = 4'b0011;
					4'd4: out = 4'b0100;
					4'd5: out = 4'b0101;
					4'd6: out = 4'b0110;
					4'd7: out = 4'b0111;
					4'd8: out = 4'b1000;
					4'd9: out = 4'b1001;
				endcase
endmodule
				
//七段显示器
module seg7_decoder(D,seg);
		input [3:0] D;
		output [6:0]seg;
		reg [6:0]seg;
		
		always @(D)
			case(D)
				4'h0: seg = ~7'h3F;
				4'h1: seg = ~7'h06;     // ---a----
				4'h2: seg = ~7'h5B;     // |      |
				4'h3: seg = ~7'h4F;     // f      b
				4'h4: seg = ~7'h66;     // |      |
				4'h5: seg = ~7'h6D;     // ---g----
				4'h6: seg = ~7'h7D;     // |      |
				4'h7: seg = ~7'h07;     // e      c
				4'h8: seg = ~7'h7F;     // |      |
				4'h9: seg = ~7'h67;     // ---d----
				default: seg =7'h00;
			endcase
endmodule

//定时控制	
module dingshi(Alarm,Min,Sec,CK);
		input [7:0] Min,Sec,CK;
		output Alarm;
		reg Alarm;
		always@(Min or Sec)
			if(Min==8'h57)///
				case(Sec)
					8'h28,
					8'h29:Alarm = CK;
					8'h30:Alarm = 1'b1;
					default: Alarm =1'b0;
				endcase
			else
				Alarm = 1'b0;
endmodule

引脚分配如下：