对复位信号多打几拍就行
`timescale 1ns/1ns
module ali16(
input clk,
input rst_n,
input d,
output reg dout
);
//*************code***********//
reg rst0;
reg rst1;
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
rst0 <= 0;
rst1 <= 0;
end
else begin
rst0 <= 1;
rst1 <= rst0;
end
end
always@(posedge clk or negedge rst1) begin
if(!rst1)
dout <= 0;
else dout <= d;
end
//*************code***********//
endmodule