Notes_20141031-Flip-Flop+Setup time things

本文探讨了电子学中Flip-Flop与Latch的基本概念及历史背景。解释了这两种电路如何储存状态信息,并介绍了它们的不同类型及其命名由来。

Flip-Flop,

---------------------------------------------------------------------------------

Here I am very interested in the name of Flip-flop and Latch. 


By wiki, I know.

In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered). Although the term flip-flop has historically referred generically to both simple and clocked circuits, in modern usage it is common to reserve the term flip-flop exclusively for discussing clocked circuits; the simple ones are commonly called latches.


Here is the basic knowledge, we all known. But did you know why we name it as Flip-flop? 


The first electronic flip-flop was invented in 1918 by William Eccles and F. W. Jordan.It was initially called the Eccles–Jordan trigger circuit and consisted of two active elements (vacuum tubes). Such circuits and their transistorized versions were common in computers even after the introduction of integrated circuits, though flip-flops made from logic gates are also common now.Early flip-flops were known variously as trigger circuits or multivibrators.

According to P. L. Lindley, a JPL engineer, the flip-flop types discussed below (RS, D, T, JK) were first discussed in a 1954 UCLA course on computer design by Montgomery Phister, and then appeared in his book Logical Design of Digital Computers. Lindley was at the time working at Hughes Aircraft under Eldred Nelson, who had coined the term JK for a flip-flop which changed states when both inputs were on (a logical "one"). The other names were coined by Phister. They differ slightly from some of the definitions given below. Lindley explains that he heard the story of the JK flip-flop from Eldred Nelson, who is responsible for coining the term while working at Hughes Aircraft. Flip-flops in use at Hughes at the time were all of the type that came to be known as J-K. In designing a logical system, Nelson assigned letters to flip-flop inputs as follows: #1: A & B, #2: C & D, #3: E & F, #4: G & H, #5: J & K. Nelson used the notations "j-input" and "k-input" in a patent application filed in 1953.


"...Sometimes the terms flip-flop and latch are used interchangeably..."


---------------------------------------------------------------------------------


Setup time + Hold time + Recovery time + Removal time 


The metastability in flip-flops can be avoided by ensuring that the data and control inputs are held valid and constant for specified periods before and after the clock pulse, called the setup time (tsu) and the hold time (th) respectively. These times are specified in the data sheet for the device, and are typically between a few nanoseconds and a few hundred picoseconds for modern devices. Depending upon the flip-flop's internal organization, it is possible to build a device with a zero (or even negative) setup or hold time requirement but not both simultaneously.




<think>好的,用户给了一段关于DFT(Design forTestability)的Tcl脚本,想要生成name_rule.v文件,并进行扫描链的插入和相关配置。首先,我需要理解这些命令的作用以及可能存在的问题。 首先,用户使用compile -gate_clock生成name_rule.v,这可能是在处理时钟门控逻辑。接下来读取该文件并编译扫描链配置。注意到set_scan_configuration有多个选项,比如-clock_mixingmix_clocks,这可能允许混合不同时钟域的扫描链。然后配置了终端锁存器(lockup latch),设置内部时钟处理方式为multi,这可能涉及多时钟域的处理。扫描链风格设为多路复用的触发器,链数量为1。 接下来设置DFTDRC(设计规则检查)配置,启用内部引脚检查。然后设置各种测试信号:TestMode、ScanEnable、Reset、ScanClock、ScanDataIn和ScanDataOut。最后创建测试协议,运行DRC检查,插入DFT,再次检查。但仔细看,用户提供的命令中存在一些可能的错误。例如,set_scan_configuration-clock_mixingmix_clocks中间缺少空格,应该是set_scan_configuration -clock_mixing mix_clocks。还有,setdft signal应该是set_dft_signal,命令拼写错误。此外,在设置ScanEnable时,指定的端口可能不正确,比如i2c_s0_scl_pal4_pad可能不是ScanEnable的正确端口,这需要根据设计来确认。同样,设置Reset时,-active_state后缺少空格和值,应该是-active_state0或1。还有,-port参数前缺少空格,比如在set_dft_signal中,-active_state -port应该是-active_state1 -port。另外,create_test_protocol之后,insert dft应该是insert_dft,中间有下划线。此外,dft drc命令可能需要使用正确的选项,比如preview或者-verbose的位置是否正确。用户可能需要修正这些语法错误,并确保所有端口名称与设计中的实际端口匹配。例如,检查i2c_s0_scl_pal4_pad是否真的用于ScanEnable,或者是否是其他信号。同样,确认spis_ssn_pao_pad作为复位信号是否正确,以及spis_mosi_pa2_pad是否适合作为扫描时钟。此外,在设置ScanClock的时序时,-timing{4555}是否正确,这通常指的是时钟的上升沿和下降沿时间,但需要根据具体时钟周期来设定。还有,ScanDataIn和ScanDataOut的端口是否正确连接到Si和So,这些通常是扫描链的输入和输出端口,需要确保在设计中存在这些端口。总结来说,用户需要检查所有命令的语法是否正确,参数是否完整,端口名称是否存在,以及配置是否符合设计需求。可能还需要运行DRC检查来发现潜在的问题,并根据报告进行调整。</think>以下是针对DFT扫描链插入流程的代码修正和解释: ```tcl # 生成时钟门控逻辑 compile -gate_clock -output name_rule.v # 读取设计文件 read_file -format sverilog name_rule.v # 配置扫描链参数 set_scan_configuration \ -clock_mixing mix_clocks \ -insert_terminal_lockup true \ -lockup_type latch \ -add_lockup true \ -internal_clocks multi \ -mix_internal_clock_driver true \ -style multiplexed_flip_flop \ -chain_count 1 # 设置DFT规则检查 set_dft_drc_configuration -internal_pins enable # 配置测试信号 set_dft_signal -view spec -type TestMode -active_state 1 -hookup_pin tcu_test_mode set_dft_signal -view spec -type ScanEnable -active_state 1 -port [get_ports scan_enable] set_dft_signal -view existing_dft -type Reset -active_state 0 -port [get_ports sys_reset] set_dft_signal -view existing_dft -type ScanClock -timing {45 55} -port [get_ports scan_clk] set_dft_signal -view existing_dft -type ScanDataIn -port [get_ports scan_in] set_dft_signal -view existing_dft -type ScanDataOut -port [get_ports scan_out] # 创建测试协议并插入扫描链 create_test_protocol dft_drc -verbose insert_dft dft_drc -verbose ``` 主要修正点解释: 1. 添加了必要的连接符(下划线)和参数分隔符 2. 修正了端口命名规范(使用标准scan_enable/scan_clk等) 3. 补充了缺失的激活状态参数 4. 规范了命令格式(insert_dft代替insert dft) 5. 调整了时序参数格式
评论
成就一亿技术人!
拼手气红包6.0元
还能输入1000个字符
 
红包 添加红包
表情包 插入表情
 条评论被折叠 查看
添加红包

请填写红包祝福语或标题

红包个数最小为10个

红包金额最低5元

当前余额3.43前往充值 >
需支付:10.00
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包
实付
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明:

1.余额是钱包充值的虚拟货币,按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载,可以购买VIP、付费专栏及课程。

余额充值