SystemVerilog：Chapter 3，Net and Variable types_3

3.3 Types and data types

        SystemVerilog provides two general groups of data types, nets and variables.

        Data types are used by software tools, such as simulators and synthesis compilers, to determine how to store data and process changes on that data.

3.3.1 Net types and variable types

        Variables are used as temporary storage for programming,actual silicon often does not need the same temporary storage, depending on the programming context in which the variable is used.

        Nets are used to connect design blocks together. A net transfers data values from a source, referred to as a driver, to a destination or receiver.

3.3.2 Two-state and four-state data types (bit and logic)

        The keyword bit defines that a variable is a 2-state data type.

        The keyword logic defines that variable or net is a 4-state data type.