interface笔记一，传统verilog的方式使用interface

1.首先写一个简单的加法器。

module counter_ud (clk,rstn,load,load_en,count);
	
	input clk;
	input rstn;     //复位端
	input load_en;  //使能端
	input  [3:0] load; 
	output [3:0] count;

	logic [3:0] load;
	logic[3:0] count;

	always @ (posedge clk or negedge rstn) begin
		
		if (!rstn)
			count <= 0;
		else begin
			if (load_en)
				count <= load;
			else
				count <= count + 1;
	    end
	end
endmodule

2.interface模块。

interface cnt_if (input clk);
	
	logic rstn;
	logic load_en;
	logic [3:0] load;
	logic [3:0] count;

endinterface

3.testbench模块。

module tb;

	logic clk;

	always #5 clk = ~clk;  //产生周期为10的clk

	cnt_if cnt_if0 (clk);  //实例化interface

    //将接口一一对应
	counter_ud u0 ( .clk      (cnt_if0.clk),
				    .rstn     (cnt_if0.rstn),
					.load_en  (cnt_if0.load_en),
					.load     (cnt_if0.load),
					.count    (cnt_if0