在Quartus-ii中出现Error: (vsim-19) Failed to access library ‘cycloneive_ver‘ at “cycloneive_ver“.

原创 于 2025-03-26 19:12:43 发布 · 562 阅读 · 5 ·
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#编辑器

一、在仿真运行时出现如上错误。

因为我的Quartus的安装和Modelsim的安装是分开进行的（出现的具体原因未知maybe）可能在关联时出现问题。

二、解决方法（非一劳永逸版）

每次新打开文件都要重新设置，不知道为什么，有大神可以解答嘛。

菜单栏点开tools,选择第二个"launch simulation library compiler"点开。

第一步

运行位置选择，modelsim的下载位置中的win64(maybe 32个人电脑配置）第二步

输出位置选择建立的该项目的文件里的simulation的qsim文件夹。

第三步

点击开始编译。

编译成功，打开仿真。vmf文件。

运行即可。

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Determining the location of the ModelSim executable... Using: D:\FPGA\modelsim\win64 To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. **** Generating the ModelSim Testbench **** quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Block1 -c Block1 --vector_source="D:/FPGA/Quartus/zuoye/Waveform.vwf" --testbench_file="D:/FPGA/Quartus/zuoye/simulation/qsim/Waveform.vwf.vt" Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition Info: Copyright (C) 2018 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Sat Dec 20 17:21:44 2025 Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Block1 -c Block1 --vector_source=D:/FPGA/Quartus/zuoye/Waveform.vwf --testbench_file=D:/FPGA/Quartus/zuoye/simulation/qsim/Waveform.vwf.vt Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Completed successfully. Completed successfully. **** Generating the functional simulation netlist **** quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="D:/FPGA/Quartus/zuoye/simulation/qsim/" Block1 -c Block1 Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition Info: Copyright (C) 2018 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Sat Dec 20 17:21:45 2025 Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=D:/FPGA/Quartus/zuoye/simulation/qsim/ Block1 -c Block1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file Block1.vo in folder "D:/FPGA/Quartus/zuoye/simulation/qsim//" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 4625 megabytes Info: Processing ended: Sat Dec 20 17:21:47 2025 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:01 Completed successfully. **** Generating the ModelSim .do script **** D:/FPGA/Quartus/zuoye/simulation/qsim/Block1.do generated. Completed successfully. **** Running the ModelSim simulation **** D:/FPGA/modelsim/win64/vsim -c -do Block1.do Reading D:/FPGA/modelsim/tcl/vsim/pref.tcl # 10.4 # do Block1.do # ** Warning: (vlib-34) Library already exists at "work". # # Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014 # Start time: 17:21:48 on Dec 20,2025 # vlog -work work Block1.vo # -- Compiling module Block1 # -- Compiling module hard_block # # Top level modules: # Block1 # End time: 17:21:48 on Dec 20,2025, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim SE-64 vlog 10.4 Compiler 2014.12 Dec 3 2014 # Start time: 17:21:48 on Dec 20,2025 # vlog -work work Waveform.vwf.vt # -- Compiling module Block1_vlg_vec_tst # # Top level modules: # Block1_vlg_vec_tst # End time: 17:21:48 on Dec 20,2025, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vsim -c -do "Block1.do" # Start time: 17:21:48 on Dec 20,2025 # ** Warning: (vsim-8891) All optimizations are turned off because the -novopt switch is in effect. This will cause your simulation to run very slowly. If you are using this switch to preserve visibility for Debug or PLI features please see the User's Manual section on Preserving Object Visibility with vopt. # # // ModelSim SE-64 10.4 Dec 3 2014 # // # // Copyright 1991-2014 Mentor Graphics Corporation # // All Rights Reserved. # // # // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION # // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS # // LICENSORS AND IS SUBJECT TO LICENSE TERMS. # // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL # // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM # // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552. # // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER # // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905. # // # Refreshing D:/FPGA/Quartus/zuoye/simulation/qsim/work.Block1_vlg_vec_tst # Loading work.Block1_vlg_vec_tst # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # Refreshing D:/FPGA/Quartus/zuoye/simulation/qsim/work.Block1 # Loading work.Block1 # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # Refreshing D:/FPGA/Quartus/zuoye/simulation/qsim/work.hard_block # Loading work.hard_block # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-3033) Block1.vo(76): Instantiation of 'cycloneive_io_obuf' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /Block1_vlg_vec_tst/i1 File: Block1.vo # Searched libraries: # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # D:/FPGA/Quartus/zuoye/simulation/qsim/work # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-3033) Block1.vo(89): Instantiation of 'cycloneive_io_ibuf' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /Block1_vlg_vec_tst/i1 File: Block1.vo # Searched libraries: # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # D:/FPGA/Quartus/zuoye/simulation/qsim/work # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-3033) Block1.vo(99): Instantiation of 'cycloneive_io_ibuf' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /Block1_vlg_vec_tst/i1 File: Block1.vo # Searched libraries: # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # D:/FPGA/Quartus/zuoye/simulation/qsim/work # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-3033) Block1.vo(109): Instantiation of 'cycloneive_io_ibuf' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /Block1_vlg_vec_tst/i1 File: Block1.vo # Searched libraries: # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # D:/FPGA/Quartus/zuoye/simulation/qsim/work # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-3033) Block1.vo(119): Instantiation of 'cycloneive_io_ibuf' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /Block1_vlg_vec_tst/i1 File: Block1.vo # Searched libraries: # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # D:/FPGA/Quartus/zuoye/simulation/qsim/work # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-3033) Block1.vo(129): Instantiation of 'cycloneive_lcell_comb' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /Block1_vlg_vec_tst/i1 File: Block1.vo # Searched libraries: # ** Error: (vsim-19) Failed to access library 'cycloneive_ver' at "cycloneive_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". # # No such file or directory. (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". # # No such file or directory. (errno = ENOENT) # D:/FPGA/Quartus/zuoye/simulation/qsim/work # Error loading design Error loading design # End time: 17:21:50 on Dec 20,2025, Elapsed time: 0:00:02 # Errors: 90, Warnings: 1 Error.
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我要变强Wow
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又遇到新的联合仿真报错啦！
Vivado2019+Modelsim仿真环境搭建(保姆式说明)
zyp626的博客
12-18 1万+
vivado配置modelsim仿真环境搭建与演示
解决vsim19报错的方法，test bench与modelsim联合仿真
liukang2004的博客
05-16 640
modelsim vsim19报错解决方案
quartus II 中解决无法使用ModelSim的问题（库文件无法打开）仿真报错 Error: (vsim-19) Failed to access library 的问题
m0_73751696的博客
10-04 2441
2.进行相关设置，值得一提的是最后的Output directory 的目录就是simulation里面的qsim。1.先打开上方任务栏 TOOLS-点击Launch Simulation Library Compiler。然后点击该页面最底下的的Start Compilation后再返回方针页面尝试。这是我在配置过程中遇到的问题并已经成功解决，希望能同样帮助到你，祝你好运。3.如果依旧不能成功，返回点击Tools-Options。你需要确保Modelsim的路径已经配置。
Modesim 仿真 ERRO VSIM-19
weixin_30819163的博客
09-27 848
今天使用Mmodesim 进行仿真时出现错误** Error: (vsim-19) Failed to access library 'bin_gary_tb' at "bin_gary_tb" 解决方法：测试文件的路径或者被调路径中含有中文或者空格。将路径中的文字或者空格去掉就OK了！ 转载于:https://www.cnblogs.com/tmluan/p/4842269.html...
Verilog HDL学习笔记-“Failed to access library ‘LED_flash_tb‘ at “LED_flash_tb“” and“Could not find ‘wor”
m0_46387889的博客
03-01 2807
quartus Ⅱ 调用modelsim-altera仿真编译器错误解释 错误1： Error: (vsim-19) Failed to access library “LED_flash_tb” at “LED_flash_tb” 如上图，之前在网上寻找答案，有说通过删除library中的work文件以及通过点击tools工具栏中 launch simulation library compiler 来解决，我在尝试过后发现都没有解决。在重新观看新手教程发现，是我在添加测试文件的过程中出了问题，如下图，
# ** Error: (vsim-19) Failed to access library ‘./rtl_work‘ at “./rtl_work“.# # No such file or di
本博客仅供免费阅读，不提供咨询服务。请勿私信。
11-15 727
# ** Error: (vsim-19) Failed to access library './rtl_work' at "./rtl_work". # # No such file or directory. (errno = ENOENT)
数字电路基础与Quartus-II入门
AI_yu3的博客
03-15 839
数字电路基础与Quartus-II入门安装Quartus-II软件和Modsim仿真出现的问题解决方法：设计D触发器使用门电路设计 安装Quartus-II软件和Modsim Quartus II 13.1的安装及使用 Modelsim SE版本的安装及使用方法 仿真出现的问题 Error: (vsim-19) Failed to access library “cyclone_ver” at “cyclone_ver” 这种类型的错误大致意思为库文件无法加载 解决方法： Quartus Prime18
modelsim仿真ISE工程时出现# ** Error: (vlog-19) Failed to access library 'rtl_work' at "rtl_work
yundanfengqing_nuc的专栏
07-21 8087
好久没有用XILINX,Quartus II等等，今天在写一个调用交织器/解交织器IP核实现交织的时候，在仿真的时候，遇到下面图1的错误：    图1 Modelsim出现的错误   找了半天解决方法，找到了下面的解答（http://blog.sina.com.cn/s/blog_6e394a3d0101722o.html）。   通常情况下一台电脑上即装有ISE，又装有q
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