基于SPI接口的FPGA远程升级实现

1.实现功能

通过处理器的SPI接口实现对FPGA固件的在线远程升级。

2. 实现原理

直接通过处理器的SPI接口来操作SPI Flash。

3. 关键注意事项

CCLK无法直接操作，需要使用STARTUPE2原语，该原语直接FPGA内部打通处理器对FLASH的CCLK引脚的操作路径。

原语配置如下：

STARTUPE2 #(

  .PROG_USR("FALSE"),  // Activate program event security feature. Requires encrypted bitstreams.

  .SIM_CCLK_FREQ(0.0)  // Set the Configuration Clock Frequency(ns) for simulation.

)

STARTUPE2_inst (

   .CFGCLK    (      ),       // 1-bit output: Configuration main clock output

   .CFGMCLK   (      ),     // 1-bit output: Configuration internal oscillator clock output

   .EOS       (      ),             // 1-bit output: Active high output signal indicating the End Of Startup.

   .PREQ      (      ),           // 1-bit output: PROGRAM request to fabric output

   .CLK       (1'b0  ),             // 1-bit input: User start-up clock input

   .GSR       (1'b0  ),             // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)

   .GTS       (1'b0  ),             // 1-bit input: Global 3-state input (GTS cannot be used for the port name)

   .KEYCLEARB (1'b1  ), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)

   .PACK      (1'b0  ),           // 1-bit input: PROGRAM acknowledge input

   .USRCCLKO  (sclk_0),   // 1-bit input: User CCLK input

                          // For Zynq-7000 devices, this input must be tied to GND

   .USRCCLKTS (1'b0  ), // 1-bit input: User CCLK 3-state enable input

                          // For Zynq-7000 devices, this input must be tied to VCC

   .USRDONEO  (1'b0  ),   // 1-bit input: User DONE pin output control

   .USRDONETS (1'b1  )  // 1-bit input: User DONE 3-state enable output

);

注意：只把处理器时钟给到.USRCCLKO  (sclk_0)即可。