Linux Command To Find the System Configuration And Hardware Information

本文详细介绍了在Linux系统中使用命令行方式获取硬件配置信息的方法,包括CPU、内存、磁盘、BIOS版本、操作系统版本等。通过运行特定命令,用户可以轻松了解系统硬件的详细情况。

Linux Command To Find the System Configuration And Hardware Information

What is the command to find the system configuration on Linux operating system using command line (text) mode?


On Linux based system most of the hardware information can be extracted from /proc file system, for example display CPU and Memory information, enter:

Tutorial details  
Difficulty Intermediate (rss)
Root privileges Yes
Requirements None
Estimated completion time 10 minutes
cat /proc/meminfo
cat /proc/cpuinfo

The following list summarizes commands to get various hardware from the system:

Linux cpu/hardware information

Use any one of the following command:
# less /proc/cpuinfo
OR
# lscpu
Sample outputs:

Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                32
On-line CPU(s) list:   0-31
Thread(s) per core:    2
Core(s) per socket:    8
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 45
Stepping:              7
CPU MHz:               1999.874
BogoMIPS:              4000.99
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              256K
L3 cache:              20480K
NUMA node0 CPU(s):     0-7,16-23
NUMA node1 CPU(s):     8-15,24-31

Linux show free and used memory in the system

Use any one of the following command:
# cat /proc/meminfo
OR
# free
# free -m
# free -mt
# free -gt

Sample outputs:

             total       used       free     shared    buffers     cached
Mem:      32911564   32665848     245716     168592     294192   29324484
-/+ buffers/cache:    3047172   29864392
Swap:       999420      81832     917588

You can also run top/htop/atop commands to see used and free memory and cpu usage and more:
# top
# htop
# atop

Find ram speed and max supported ram by the server

# dmidecode --type 17
# lshw -short -C memory
perl memconf.v3.06.pl -v

Sample outputs:

memconf:  V3.06 17-Feb-2015 http://sourceforge.net/projects/memconf/
hostname: server1
manufacturer: Supermicro
model:    X9DRi-LN4+/X9DR3-LN4+ (2 X Eight-Core Hyper-Threaded Intel(R) Xeon(R) E5-2650 0 @ 2.00GHz)
BusyBox v1.21.1
is, Ubuntu 14.04.2 LTS, 64-bit kernel, Linux 3.13.0-46-generic
CPU 1: Intel(R) Xeon(R) E5-2650 0 @ 2.00GHz cpu, system freq: 100MHz
CPU 2: Intel(R) Xeon(R) E5-2650 0 @ 2.00GHz cpu, system freq: 100MHz
Memory Error Correction: Multi-bit ECC
Maximum Memory: 786432MB (768GB)
P1-DIMMA1 P0_Node0_Channel0_Dimm0: 4096MB 1600MHz Registered (Buffered) DDR3 DIMM, Kingston SL4D316R11D8HE
P1-DIMMB1 P0_Node0_Channel1_Dimm0: 4096MB 1600MHz Registered (Buffered) DDR3 DIMM, Kingston SL4D316R11D8HE
P1-DIMMC1 P0_Node0_Channel2_Dimm0: 4096MB 1600MHz Registered (Buffered) DDR3 DIMM, Kingston SL4D316R11D8HE
P1-DIMMD1 P0_Node0_Channel3_Dimm0: 4096MB 1600MHz Registered (Buffered) DDR3 DIMM, Kingston SL4D316R11D8HE
P2-DIMME1 P1_Node1_Channel0_Dimm0: 4096MB 1600MHz Registered (Buffered) DDR3 DIMM, Kingston SL4D316R11D8HE
P2-DIMMF1 P1_Node1_Channel1_Dimm0: 4096MB 1600MHz Registered (Buffered) DDR3 DIMM, Kingston SL4D316R11D8HE
P2-DIMMG1 P1_Node1_Channel2_Dimm0: 4096MB 1600MHz Registered (Buffered) DDR3 DIMM, Kingston SL4D316R11D8HE
P2-DIMMH1 P1_Node1_Channel3_Dimm0: 4096MB 1600MHz Registered (Buffered) DDR3 DIMM, Kingston SL4D316R11D8HE

Linux find out the current running kernel version

Type the following command:
# cat /proc/version
Sample outputs:

Linux version 3.2.0-43-generic (buildd@batsu) (gcc version 4.6.3 (Ubuntu/Linaro 4.6.3-1ubuntu5) ) #68-Ubuntu SMP Wed May 15 03:33:33 UTC 2013

OR use the following command:
# uname -mrs
# uname -a

Find out information about the Linux distribution and version

# lsb_release -a
Sample outputs:

No LSB modules are available.
Distributor ID:	Ubuntu
Description:	Ubuntu 12.04.2 LTS
Release:	12.04
Codename:	precise

OR use the following command:
$ cat /etc/*release*
Sample outputs:

Red Hat Enterprise Linux Server release 6.4 (Santiago)

List all PCI devices

# lspci
Sample outputs:

00:00.0 Host bridge: Intel Corporation Xeon E5/Core i7 DMI2 (rev 07)
00:01.0 PCI bridge: Intel Corporation Xeon E5/Core i7 IIO PCI Express Root Port 1a (rev 07)
00:01.1 PCI bridge: Intel Corporation Xeon E5/Core i7 IIO PCI Express Root Port 1b (rev 07)
00:02.0 PCI bridge: Intel Corporation Xeon E5/Core i7 IIO PCI Express Root Port 2a (rev 07)
00:03.0 PCI bridge: Intel Corporation Xeon E5/Core i7 IIO PCI Express Root Port 3a in PCI Express Mode (rev 07)
00:04.0 System peripheral: Intel Corporation Xeon E5/Core i7 DMA Channel 0 (rev 07)
00:04.1 System peripheral: Intel Corporation Xeon E5/Core i7 DMA Channel 1 (rev 07)
00:04.2 System peripheral: Intel Corporation Xeon E5/Core i7 DMA Channel 2 (rev 07)
00:04.3 System peripheral: Intel Corporation Xeon E5/Core i7 DMA Channel 3 (rev 07)
00:04.4 System peripheral: Intel Corporation Xeon E5/Core i7 DMA Channel 4 (rev 07)
00:04.5 System peripheral: Intel Corporation Xeon E5/Core i7 DMA Channel 5 (rev 07)
00:04.6 System peripheral: Intel Corporation Xeon E5/Core i7 DMA Channel 6 (rev 07)
00:04.7 System peripheral: Intel Corporation Xeon E5/Core i7 DMA Channel 7 (rev 07)
00:05.0 System peripheral: Intel Corporation Xeon E5/Core i7 Address Map, VTd_Misc, System Management (rev 07)
00:05.2 System peripheral: Intel Corporation Xeon E5/Core i7 Control Status and Global Errors (rev 07)
00:05.4 PIC: Intel Corporation Xeon E5/Core i7 I/O APIC (rev 07)
00:11.0 PCI bridge: Intel Corporation C600/X79 series chipset PCI Express Virtual Root Port (rev 06)
00:16.0 Communication controller: Intel Corporation C600/X79 series chipset MEI Controller #1 (rev 05)
00:16.1 Communication controller: Intel Corporation C600/X79 series chipset MEI Controller #2 (rev 05)
00:1a.0 USB controller: Intel Corporation C600/X79 series chipset USB2 Enhanced Host Controller #2 (rev 06)
00:1c.0 PCI bridge: Intel Corporation C600/X79 series chipset PCI Express Root Port 1 (rev b6)
00:1d.0 USB controller: Intel Corporation C600/X79 series chipset USB2 Enhanced Host Controller #1 (rev 06)
00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev a6)
00:1f.0 ISA bridge: Intel Corporation C600/X79 series chipset LPC Controller (rev 06)
00:1f.2 SATA controller: Intel Corporation C600/X79 series chipset 6-Port SATA AHCI Controller (rev 06)
00:1f.3 SMBus: Intel Corporation C600/X79 series chipset SMBus Host Controller (rev 06)
00:1f.6 Signal processing controller: Intel Corporation C600/X79 series chipset Thermal Management Controller (rev 06)
06:00.0 Ethernet controller: Intel Corporation I350 Gigabit Network Connection (rev 01)
06:00.1 Ethernet controller: Intel Corporation I350 Gigabit Network Connection (rev 01)
06:00.2 Ethernet controller: Intel Corporation I350 Gigabit Network Connection (rev 01)
06:00.3 Ethernet controller: Intel Corporation I350 Gigabit Network Connection (rev 01)
08:01.0 VGA compatible controller: Matrox Electronics Systems Ltd. MGA G200eW WPCM450 (rev 0a)
7f:08.0 System peripheral: Intel Corporation Xeon E5/Core i7 QPI Link 0 (rev 07)
7f:08.3 System peripheral: Intel Corporation Xeon E5/Core i7 QPI Link Reut 0 (rev 07)
7f:08.4 System peripheral: Intel Corporation Xeon E5/Core i7 QPI Link Reut 0 (rev 07)
7f:09.0 System peripheral: Intel Corporation Xeon E5/Core i7 QPI Link 1 (rev 07)
7f:09.3 System peripheral: Intel Corporation Xeon E5/Core i7 QPI Link Reut 1 (rev 07)
7f:09.4 System peripheral: Intel Corporation Xeon E5/Core i7 QPI Link Reut 1 (rev 07)
7f:0a.0 System peripheral: Intel Corporation Xeon E5/Core i7 Power Control Unit 0 (rev 07)
7f:0a.1 System peripheral: Intel Corporation Xeon E5/Core i7 Power Control Unit 1 (rev 07)
7f:0a.2 System peripheral: Intel Corporation Xeon E5/Core i7 Power Control Unit 2 (rev 07)
7f:0a.3 System peripheral: Intel Corporation Xeon E5/Core i7 Power Control Unit 3 (rev 07)
7f:0b.0 System peripheral: Intel Corporation Xeon E5/Core i7 Interrupt Control Registers (rev 07)
7f:0b.3 System peripheral: Intel Corporation Xeon E5/Core i7 Semaphore and Scratchpad Configuration Registers (rev 07)
7f:0c.0 System peripheral: Intel Corporation Xeon E5/Core i7 Unicast Register 0 (rev 07)
7f:0c.1 System peripheral: Intel Corporation Xeon E5/Core i7 Unicast Register 0 (rev 07)
7f:0c.2 System peripheral: Intel Corporation Xeon E5/Core i7 Unicast Register 0 (rev 07)
7f:0c.3 System peripheral: Intel Corporation Xeon E5/Core i7 Unicast Register 0 (rev 07)
7f:0c.6 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller System Address Decoder 0 (rev 07)
7f:0c.7 System peripheral: Intel Corporation Xeon E5/Core i7 System Address Decoder (rev 07)
7f:0d.0 System peripheral: Intel Corporation Xeon E5/Core i7 Unicast Register 0 (rev 07)
7f:0d.1 System peripheral: Intel Corporation Xeon E5/Core i7 Unicast Register 0 (rev 07)
7f:0d.2 System peripheral: Intel Corporation Xeon E5/Core i7 Unicast Register 0 (rev 07)
7f:0d.3 System peripheral: Intel Corporation Xeon E5/Core i7 Unicast Register 0 (rev 07)
7f:0d.6 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller System Address Decoder 1 (rev 07)
7f:0e.0 System peripheral: Intel Corporation Xeon E5/Core i7 Processor Home Agent (rev 07)
7f:0e.1 Performance counters: Intel Corporation Xeon E5/Core i7 Processor Home Agent Performance Monitoring (rev 07)
7f:0f.0 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller Registers (rev 07)
7f:0f.1 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller RAS Registers (rev 07)
7f:0f.2 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller Target Address Decoder 0 (rev 07)
7f:0f.3 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller Target Address Decoder 1 (rev 07)
7f:0f.4 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller Target Address Decoder 2 (rev 07)
7f:0f.5 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller Target Address Decoder 3 (rev 07)
7f:0f.6 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller Target Address Decoder 4 (rev 07)
7f:10.0 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller Channel 0-3 Thermal Control 0 (rev 07)
7f:10.1 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller Channel 0-3 Thermal Control 1 (rev 07)
7f:10.2 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller ERROR Registers 0 (rev 07)
7f:10.3 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller ERROR Registers 1 (rev 07)
7f:10.4 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller Channel 0-3 Thermal Control 2 (rev 07)
7f:10.5 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller Channel 0-3 Thermal Control 3 (rev 07)
7f:10.6 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller ERROR Registers 2 (rev 07)
7f:10.7 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller ERROR Registers 3 (rev 07)
7f:11.0 System peripheral: Intel Corporation Xeon E5/Core i7 DDRIO (rev 07)
7f:13.0 System peripheral: Intel Corporation Xeon E5/Core i7 R2PCIe (rev 07)
7f:13.1 Performance counters: Intel Corporation Xeon E5/Core i7 Ring to PCI Express Performance Monitor (rev 07)
7f:13.4 Performance counters: Intel Corporation Xeon E5/Core i7 QuickPath Interconnect Agent Ring Registers (rev 07)
7f:13.5 Performance counters: Intel Corporation Xeon E5/Core i7 Ring to QuickPath Interconnect Link 0 Performance Monitor (rev 07)
7f:13.6 System peripheral: Intel Corporation Xeon E5/Core i7 Ring to QuickPath Interconnect Link 1 Performance Monitor (rev 07)
80:01.0 PCI bridge: Intel Corporation Xeon E5/Core i7 IIO PCI Express Root Port 1a (rev 07)
80:02.0 PCI bridge: Intel Corporation Xeon E5/Core i7 IIO PCI Express Root Port 2a (rev 07)
80:03.0 PCI bridge: Intel Corporation Xeon E5/Core i7 IIO PCI Express Root Port 3a in PCI Express Mode (rev 07)
80:04.0 System peripheral: Intel Corporation Xeon E5/Core i7 DMA Channel 0 (rev 07)
80:04.1 System peripheral: Intel Corporation Xeon E5/Core i7 DMA Channel 1 (rev 07)
80:04.2 System peripheral: Intel Corporation Xeon E5/Core i7 DMA Channel 2 (rev 07)
80:04.3 System peripheral: Intel Corporation Xeon E5/Core i7 DMA Channel 3 (rev 07)
80:04.4 System peripheral: Intel Corporation Xeon E5/Core i7 DMA Channel 4 (rev 07)
80:04.5 System peripheral: Intel Corporation Xeon E5/Core i7 DMA Channel 5 (rev 07)
80:04.6 System peripheral: Intel Corporation Xeon E5/Core i7 DMA Channel 6 (rev 07)
80:04.7 System peripheral: Intel Corporation Xeon E5/Core i7 DMA Channel 7 (rev 07)
80:05.0 System peripheral: Intel Corporation Xeon E5/Core i7 Address Map, VTd_Misc, System Management (rev 07)
80:05.2 System peripheral: Intel Corporation Xeon E5/Core i7 Control Status and Global Errors (rev 07)
80:05.4 PIC: Intel Corporation Xeon E5/Core i7 I/O APIC (rev 07)
81:00.0 RAID bus controller: Adaptec AAC-RAID (rev 09)
ff:08.0 System peripheral: Intel Corporation Xeon E5/Core i7 QPI Link 0 (rev 07)
ff:08.3 System peripheral: Intel Corporation Xeon E5/Core i7 QPI Link Reut 0 (rev 07)
ff:08.4 System peripheral: Intel Corporation Xeon E5/Core i7 QPI Link Reut 0 (rev 07)
ff:09.0 System peripheral: Intel Corporation Xeon E5/Core i7 QPI Link 1 (rev 07)
ff:09.3 System peripheral: Intel Corporation Xeon E5/Core i7 QPI Link Reut 1 (rev 07)
ff:09.4 System peripheral: Intel Corporation Xeon E5/Core i7 QPI Link Reut 1 (rev 07)
ff:0a.0 System peripheral: Intel Corporation Xeon E5/Core i7 Power Control Unit 0 (rev 07)
ff:0a.1 System peripheral: Intel Corporation Xeon E5/Core i7 Power Control Unit 1 (rev 07)
ff:0a.2 System peripheral: Intel Corporation Xeon E5/Core i7 Power Control Unit 2 (rev 07)
ff:0a.3 System peripheral: Intel Corporation Xeon E5/Core i7 Power Control Unit 3 (rev 07)
ff:0b.0 System peripheral: Intel Corporation Xeon E5/Core i7 Interrupt Control Registers (rev 07)
ff:0b.3 System peripheral: Intel Corporation Xeon E5/Core i7 Semaphore and Scratchpad Configuration Registers (rev 07)
ff:0c.0 System peripheral: Intel Corporation Xeon E5/Core i7 Unicast Register 0 (rev 07)
ff:0c.1 System peripheral: Intel Corporation Xeon E5/Core i7 Unicast Register 0 (rev 07)
ff:0c.2 System peripheral: Intel Corporation Xeon E5/Core i7 Unicast Register 0 (rev 07)
ff:0c.3 System peripheral: Intel Corporation Xeon E5/Core i7 Unicast Register 0 (rev 07)
ff:0c.6 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller System Address Decoder 0 (rev 07)
ff:0c.7 System peripheral: Intel Corporation Xeon E5/Core i7 System Address Decoder (rev 07)
ff:0d.0 System peripheral: Intel Corporation Xeon E5/Core i7 Unicast Register 0 (rev 07)
ff:0d.1 System peripheral: Intel Corporation Xeon E5/Core i7 Unicast Register 0 (rev 07)
ff:0d.2 System peripheral: Intel Corporation Xeon E5/Core i7 Unicast Register 0 (rev 07)
ff:0d.3 System peripheral: Intel Corporation Xeon E5/Core i7 Unicast Register 0 (rev 07)
ff:0d.6 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller System Address Decoder 1 (rev 07)
ff:0e.0 System peripheral: Intel Corporation Xeon E5/Core i7 Processor Home Agent (rev 07)
ff:0e.1 Performance counters: Intel Corporation Xeon E5/Core i7 Processor Home Agent Performance Monitoring (rev 07)
ff:0f.0 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller Registers (rev 07)
ff:0f.1 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller RAS Registers (rev 07)
ff:0f.2 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller Target Address Decoder 0 (rev 07)
ff:0f.3 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller Target Address Decoder 1 (rev 07)
ff:0f.4 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller Target Address Decoder 2 (rev 07)
ff:0f.5 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller Target Address Decoder 3 (rev 07)
ff:0f.6 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller Target Address Decoder 4 (rev 07)
ff:10.0 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller Channel 0-3 Thermal Control 0 (rev 07)
ff:10.1 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller Channel 0-3 Thermal Control 1 (rev 07)
ff:10.2 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller ERROR Registers 0 (rev 07)
ff:10.3 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller ERROR Registers 1 (rev 07)
ff:10.4 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller Channel 0-3 Thermal Control 2 (rev 07)
ff:10.5 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller Channel 0-3 Thermal Control 3 (rev 07)
ff:10.6 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller ERROR Registers 2 (rev 07)
ff:10.7 System peripheral: Intel Corporation Xeon E5/Core i7 Integrated Memory Controller ERROR Registers 3 (rev 07)
ff:11.0 System peripheral: Intel Corporation Xeon E5/Core i7 DDRIO (rev 07)
ff:13.0 System peripheral: Intel Corporation Xeon E5/Core i7 R2PCIe (rev 07)
ff:13.1 Performance counters: Intel Corporation Xeon E5/Core i7 Ring to PCI Express Performance Monitor (rev 07)
ff:13.4 Performance counters: Intel Corporation Xeon E5/Core i7 QuickPath Interconnect Agent Ring Registers (rev 07)
ff:13.5 Performance counters: Intel Corporation Xeon E5/Core i7 Ring to QuickPath Interconnect Link 0 Performance Monitor (rev 07)
ff:13.6 System peripheral: Intel Corporation Xeon E5/Core i7 Ring to QuickPath Interconnect Link 1 Performance Monitor (rev 07)

List all USB devices

# lsusb
Sample outputs:

Bus 002 Device 002: ID 8087:0024 Intel Corp. Integrated Rate Matching Hub
Bus 002 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Bus 001 Device 003: ID 0557:2221 ATEN International Co., Ltd Winbond Hermon
Bus 001 Device 002: ID 8087:0024 Intel Corp. Integrated Rate Matching Hub
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub

List all block devices (hard disks, cdrom, and others)

# lsblk
Sample outputs:

sda      8:0    1 372.3G  0 disk
|-sda1   8:1    1   243M  0 part /boot
|-sda2   8:2    1     1K  0 part
|-sda5   8:5    1   976M  0 part [SWAP]
`-sda6   8:6    1 371.1G  0 part /
sr0     11:0    1  1024M  0 rom
loop0    7:0    0     4G  0 loop /jails/tmp

Display installed hard disk and size

# fdisk -l | grep '^Disk /dev/'
Sample outputs:

Disk /dev/sda: 399.7 GB, 399717171200 bytes

Display information about hardware RAID

See info about Adaptec hardware RAID:
# arcconf getconfig DEV
# /usr/StorMan/arcconf getconfig 1

See info about 3ware hardware RAID:
# tw_cli /dev show
# tw_cli /c0 show

Say hello to lshw

The lshw is a small command line tool to extract detailed information on the hardware configuration of the machine. It can report exact memory configuration, firmware version, mainboard configuration, CPU version and speed, cache configuration, bus speed, etc. on DMI-capable x86 or IA-64 systems and on some PowerPC machines (PowerMac G4 is known to work):
# lshw | more
# lshw -html > output.htmlq
# lshw -short | less

Sample outputs:

H/W path          Device      Class          Description
========================================================
                              system         X9DRi-LN4+/X9DR3-LN4+ (To be filled by O.E.M.)
/0                            bus            X9DRi-LN4+/X9DR3-LN4+
/0/0                          memory         64KiB BIOS
/0/4                          processor      Intel(R) Xeon(R) CPU E5-2650 0 @ 2.00GHz
/0/4/5                        memory         512KiB L1 cache
/0/4/6                        memory         2MiB L2 cache
/0/4/7                        memory         20MiB L3 cache
/0/6                          processor      Intel(R) Xeon(R) CPU E5-2650 0 @ 2.00GHz
/0/6/9                        memory         512KiB L1 cache
/0/6/a                        memory         2MiB L2 cache
/0/6/b                        memory         20MiB L3 cache
/0/2f                         memory         System Memory
/0/2f/0                       memory         4GiB DIMM DDR3 1600 MHz (0.6 ns)
/0/2f/1                       memory         DIMM Synchronous [empty]
/0/2f/2                       memory         DIMM Synchronous [empty]
/0/2f/3                       memory         4GiB DIMM DDR3 1600 MHz (0.6 ns)
/0/2f/4                       memory         DIMM Synchronous [empty]
/0/2f/5                       memory         DIMM Synchronous [empty]
/0/2f/6                       memory         4GiB DIMM DDR3 1600 MHz (0.6 ns)
....
...
..
/0/1                          bridge         Xeon E5/Core i7 IIO PCI Express Root Port 1a
/0/1/0            scsi0       storage        AAC-RAID
/0/1/0/0.0.0      /dev/sda    disk           399GB SCSI Disk
/0/1/0/0.0.0/1    /dev/sda1   volume         243MiB Linux filesystem partition
/0/1/0/0.0.0/2    /dev/sda2   volume         372GiB Extended partition
/0/1/0/0.0.0/2/5  /dev/sda5   volume         976MiB Linux swap / Solaris partition
/0/1/0/0.0.0/2/6  /dev/sda6   volume         371GiB Linux filesystem partition
/0/1/0/1.0.0                  disk           SCSI Disk
/0/1/0/1.1.0                  disk           SCSI Disk
/0/1/0/1.2.0                  disk           SCSI Disk
/0/1/0/1.3.0                  disk           SCSI Disk
...
..
...
/0/68             scsi5       storage
/0/68/0.0.0       /dev/cdrom  disk           DV-28S-W
/1                            power          PWS-605P-1H
/2                vethWKP76N  network        Ethernet interface
/3                veth1N2SWB  network        Ethernet interface
/4                veth8L2A3F  network        Ethernet interface
/5                bond0       network        Ethernet interface
 

Dump all hardware information

Type the following command to see your motherboard, cpu, vendor, serial-numbers, RAM, disks, and other information directly from the system BIOS:
# dmidecode | less
Sample outputs:

# dmidecode 2.12
SMBIOS 2.7 present.
155 structures occupying 7700 bytes.
Table at 0x000EC440.
 
Handle 0x0000, DMI type 0, 24 bytes
BIOS Information
        Vendor: American Megatrends Inc.
        Version: 3.0b
        Release Date: 05/27/2014
        Address: 0xF0000
        Runtime Size: 64 kB
        ROM Size: 12288 kB
        Characteristics:
                PCI is supported
                BIOS is upgradeable
                BIOS shadowing is allowed
                Boot from CD is supported
                Selectable boot is supported
                BIOS ROM is socketed
                EDD is supported
                Print screen service is supported (int 5h)
                8042 keyboard services are supported (int 9h)
                Serial services are supported (int 14h)
                Printer services are supported (int 17h)
                ACPI is supported
                USB legacy is supported
                BIOS boot specification is supported
                Function key-initiated network boot is supported
                Targeted content distribution is supported
                UEFI is supported
        BIOS Revision: 3.11
 
Handle 0x0001, DMI type 1, 27 bytes
System Information
        Manufacturer: Supermicro
        Product Name: X9DRi-LN4+/X9DR3-LN4+
        Version: 0123456789
        Serial Number: 0123456789
        UUID: 00000000-0000-0000-0000-0025902E1590
        Wake-up Type: Power Switch
        SKU Number: To be filled by O.E.M.
        Family: To be filled by O.E.M.
 
Handle 0x0002, DMI type 2, 15 bytes
Base Board Information
        Manufacturer: Supermicro
....
..
...
 
Handle 0x00AB, DMI type 13, 22 bytes
BIOS Language Information
        Language Description Format: Long
        Installable Languages: 1
                en|US|iso8859-1
        Currently Installed Language: en|US|iso8859-1
 
Handle 0x00AE, DMI type 127, 4 bytes
End Of Table
 
Streaming MAVLink Messages This tutorial demonstrates how to stream a uORB message as a MAVLink message, and applies to both standard and custom messages. Overview MAVLink messages are streamed using a streaming class, derived from MavlinkStream, that has been added to the PX4 stream list. The class has framework methods that you implement so PX4 can get information it needs from the generated MAVLink message definition. It also has a send() method that is called each time the message needs to be sent — you override this to copy information from a uORB subscription to the MAVLink message object that is to be sent. Once you have created a streaming class the corresponding message can be streamed on request. You can also configure PX4 to stream the message by default, depending on the MAVLink configuration. Preconditions Generally you will already have a uORB message that contains information you'd like to stream and a definition of a MAVLink message that you'd like to stream it with. For this example we're going to assume that you want to stream the (existing) BatteryStatus uORB message to a new MAVLink battery status message, which we will name BATTERY_STATUS_DEMO. Copy this BATTERY_STATUS_DEMO message into the message section of development.xml in your PX4 source code, which will be located at: \src\modules\mavlink\mavlink\message_definitions\v1.0\development.xml. <message id="11514" name="BATTERY_STATUS_DEMO"> <description>Simple demo battery.</description> <field type="uint8_t" name="id" instance="true">Battery ID</field> <field type="int16_t" name="temperature" units="cdegC" invalid="INT16_MAX">Temperature of the whole battery pack (not internal electronics). INT16_MAX field not provided.</field> <field type="uint8_t" name="percent_remaining" units="%" invalid="UINT8_MAX">Remaining battery energy. Values: [0-100], UINT8_MAX: field not provided.</field> </message> INFO Note that this is a cut-down version of the not-yet-implemented BATTERY_STATUS_V2 message with randomly chosen unused id of 11514. Here we've put the message in development.xml, which is fine for testing and if the message is intended to eventually be part of the standard message set, but you might also put a custom message in its own dialect file. Build PX4 for SITL and confirm that the associated message is generated in /build/px4_sitl_default/mavlink/development/mavlink_msg_battery_status_demo.h. Because BatteryStatus already exists you will not need to do anything to create or build it. Define the Streaming Class First create a file named BATTERY_STATUS_DEMO.hpp for your streaming class (named after the message to stream) inside the /src/modules/mavlink/streams directory. Add the headers for the uORB message(s) to the top of the file (the required MAVLink headers should already be available): #include <uORB/topics/battery_status.h> INFO The uORB topic's snake-case header file is generated from the CamelCase uORB filename at build time. Then copy the streaming class definition below into the file: class MavlinkStreamBatteryStatusDemo : public MavlinkStream { public: static MavlinkStream *new_instance(Mavlink *mavlink) { return new MavlinkStreamBatteryStatusDemo(mavlink); } const char *get_name() const { return MavlinkStreamBatteryStatusDemo::get_name_static(); } static const char *get_name_static() { return "BATTERY_STATUS_DEMO"; } static uint16_t get_id_static() { return MAVLINK_MSG_ID_BATTERY_STATUS_DEMO; } uint16_t get_id() { return get_id_static(); } unsigned get_size() { return MAVLINK_MSG_ID_BATTERY_STATUS_DEMO_LEN + MAVLINK_NUM_NON_PAYLOAD_BYTES; } private: //Subscription to array of uORB battery status instances uORB::SubscriptionMultiArray<battery_status_s, battery_status_s::MAX_INSTANCES> _battery_status_subs{ORB_ID::battery_status}; // SubscriptionMultiArray subscription is needed because battery has multiple instances. // uORB::Subscription is used to subscribe to a single-instance topic /* do not allow top copying this class */ MavlinkStreamBatteryStatusDemo(MavlinkStreamBatteryStatusDemo &); MavlinkStreamBatteryStatusDemo& operator = (const MavlinkStreamBatteryStatusDemo &); protected: explicit MavlinkStreamBatteryStatusDemo(Mavlink *mavlink) : MavlinkStream(mavlink) {} bool send() override { bool updated = false; // Loop through _battery_status_subs (subscription to array of BatteryStatus instances) for (auto &battery_sub : _battery_status_subs) { // battery_status_s is a struct that can hold the battery object topic battery_status_s battery_status; // Update battery_status and publish only if the status has changed if (battery_sub.update(&battery_status)) { // mavlink_battery_status_demo_t is the MAVLink message object mavlink_battery_status_demo_t bat_msg{}; bat_msg.id = battery_status.id - 1; bat_msg.percent_remaining = (battery_status.connected) ? roundf(battery_status.remaining * 100.f) : -1; // check if temperature valid if (battery_status.connected && PX4_ISFINITE(battery_status.temperature)) { bat_msg.temperature = battery_status.temperature * 100.f; } else { bat_msg.temperature = INT16_MAX; } //Send the message mavlink_msg_battery_status_demo_send_struct(_mavlink->get_channel(), &bat_msg); updated = true; } } return updated; } }; Most streaming classes are very similar (see examples in /src/modules/mavlink/streams): The streaming class derives from MavlinkStream and is named using the pattern MavlinkStream<CamelCaseMessageName>. The public definitions are "near-boilerplate", allowing PX4 to get an instance of the class (new_instance()), and then to use it to fetch the name, id, and size of the message from the MAVLink headers (get_name(), get_name_static(), get_id_static(), get_id(), get_size()). For your own streaming classes these can just be copied and modified to match the values for your MAVLink message. The private definitions subscribe to the uORB topics that need to be published. In this case the uORB topic has multiple instances: one for each battery. We use uORB::SubscriptionMultiArray to get an array of battery status subscriptions. Here we also define constructors to prevent the definition being copied. The protected section is where the important work takes place! Here we override the send() method, copying values from the subscribed uORB topic(s) into appropriate fields in the MAVLink message, and then send the message. In this particular example we have an array of uORB instances _battery_status_subs (because we have multiple batteries). We iterate the array and use update() on each subscription to check if the associated battery instance has changed (and update a structure with the current data). This allows us to send the MAVLink message only if the associated battery uORB topic has changed: // Struct to hold current topic data. battery_status_s battery_status; // update() populates battery_status and returns true if the status has changed if (battery_sub.update(&battery_status)) { // Use battery_status to populate message and send } If wanted to send a MAVLink message whether or not the data changed, we could instead use copy() as shown: battery_status_s battery_status; battery_sub.copy(&battery_status); INFO For a single-instance topic like VehicleStatus we would subscribe like this: // Create subscription _vehicle_status_sub uORB::Subscription _vehicle_status_sub{ORB_ID(vehicle_status)}; And we could use the resulting subscription in the same way with update or copy. vehicle_status_s vehicle_status{}; // vehicle_status_s is the definition of the uORB topic if (_vehicle_status_sub.update(&vehicle_status)) { // Use the vehicle_status as it has been updated. } Next we include our new class in mavlink_messages.cpp. Add the line below to the part of the file where all the other streams are included: #include "streams/BATTERY_STATUS_DEMO.hpp" Finally append the stream class to the streams_list at the bottom of mavlink_messages.cpp StreamListItem *streams_list[] = { ... #if defined(BATTERY_STATUS_DEMO_HPP) create_stream_list_item<MavlinkStreamBatteryStatusDemo>(), #endif // BATTERY_STATUS_DEMO_HPP ... } The class is now available for streaming, but won't be streamed by default. We cover that in the next sections. Streaming by Default The easiest way to stream your messages by default (as part of a build) is to add them to mavlink_main.cpp in the appropriate message group. If you search in the file you'll find groups of messages defined in a switch statement: MAVLINK_MODE_NORMAL: Streamed to a GCS. MAVLINK_MODE_ONBOARD: Streamed to a companion computer on a fast link, such as Ethernet MAVLINK_MODE_ONBOARD_LOW_BANDWIDTH: Streamed to a companion computer for re-routing to a reduced-traffic link, such as a GCS. MAVLINK_MODE_GIMBAL: Streamed to a gimbal MAVLINK_MODE_EXTVISION: Streamed to an external vision system MAVLINK_MODE_EXTVISIONMIN: Streamed to an external vision system on a slower link MAVLINK_MODE_OSD: Streamed to an OSD, such as an FPV headset. MAVLINK_MODE_CUSTOM: Stream nothing by default. Used when configuring streaming using MAVLink. MAVLINK_MODE_MAGIC: Same as MAVLINK_MODE_CUSTOM MAVLINK_MODE_CONFIG: Streaming over USB with higher rates than MAVLINK_MODE_NORMAL. MAVLINK_MODE_MINIMAL: Stream a minimal set of messages. Normally used for poor telemetry links. MAVLINK_MODE_IRIDIUM: Streamed to an iridium satellite phone Normally you'll be testing on a GCS, so you could just add the message to the MAVLINK_MODE_NORMAL case using the configure_stream_local() method. For example, to stream CA_TRAJECTORY at 5 Hz: case MAVLINK_MODE_CONFIG: // USB // Note: streams requiring low latency come first ... configure_stream_local("BATTERY_STATUS_DEMO", 5.0f); ... It is also possible to add a stream by calling the mavlink module with the stream argument in a startup script. For example, you might add the following line to /ROMFS/px4fmu_common/init.d-posix/px4-rc.mavlink in order to stream BATTERY_STATUS_DEMO at 50Hz on UDP port 14556 (-r configures the streaming rate and -u identifies the MAVLink channel on UDP port 14556). mavlink stream -r 50 -s BATTERY_STATUS_DEMO -u 14556 Streaming on Request Some messages are only needed once, when particular hardware is connected, or under other circumstances. In order to avoid clogging communications links with messages that aren't needed you may not stream all messages by default, even at low rate. If you needed, a GCS or other MAVLink API can request that particular messages are streamed at a particular rate using MAV_CMD_SET_MESSAGE_INTERVAL. A particular message can be requested just once using MAV_CMD_REQUEST_MESSAGE.
09-15
<think> 我们正在处理的问题是如何将uORB消息作为MAVLink消息进行流式传输。以下是详细的步骤: 1. **添加消息定义**: - 如果自定义消息,需要在MAVLink的XML文件中定义新的消息(通常在`development.xml`或自定义XML中)。 - 例如,假设我们有一个uORB消息`vehicle_gps_position`,我们想将其作为MAVLink消息流式传输。但是,实际上`vehicle_gps_position`对应的MAVLink消息已经存在(如`GPS_RAW_INT`)。如果需要定义新的消息,则按照MAVLink规范定义。 2. **生成消息头**: - 将定义好的XML文件放入PX4源码的`src/modules/mavlink/mavlink/message_definitions/v1.0/`目录下(如果是自定义消息,可以放在这里,但标准消息应该提交到MAVLink官方仓库)。 - 编译PX4时,构建系统会自动生成对应的C语言头文件(在build目录的`mavlink`子目录中)。 3. **实现消息发送器**: - 在PX4中,MAVLink消息的发送通常通过`mavlink_messages.cpp`或自定义模块实现。 - 步骤: a. 订阅uORB消息(例如`vehicle_gps_position_s`)。 b. 将uORB消息的数据转换为MAVLink消息格式。 c. 使用MAVLink库函数打包消息。 d. 通过MAVLink通道发送(例如`mavlink_msg_gps_raw_int_send_struct`)。 4. **配置默认流式传输**: - 默认流式传输在PX4中通过设置流速率(stream rate)来实现。可以在启动脚本(如`rc.mavlink`)中设置,或者通过参数(如`MAV_0_CONFIG`等)来配置。 - 例如,使用`mavlink stream`命令设置特定消息的流速率: ```bash mavlink stream -u <port> -s <message_name> -r <rate_in_hz> ``` - 或者在代码中设置默认速率:在`mavlink_main.cpp`中,有默认的流配置表(`streams_list`),可以添加你的消息和默认速率。 5. **实现按需流式传输**: - 按需流式传输通常通过MAVLink命令(`MAV_CMD_SET_MESSAGE_INTERVAL`)来动态设置消息的流速率。 - 在PX4中,这个命令已经在`mavlink_receiver.cpp`中处理。当你发送一个`MAV_CMD_SET_MESSAGE_INTERVAL`命令时,它会设置指定消息ID的流速率。 - 例如,地面站可以发送一个命令来请求`GPS_RAW_INT`消息以特定的速率发送。 6. **实现消息接收**(如果需要): - 接收MAVLink消息通常在`mavlink_receiver.cpp`中处理。你可以添加一个case来处理新的消息ID,然后将其转换为uORB消息并发布。 下面我们详细说明关键步骤: ### 步骤1:添加消息定义(如果需要新消息) 假设我们需要定义一个新的MAVLink消息,例如`MY_GPS`(仅举例,实际中可能不需要,因为已有标准消息)。我们编辑`development.xml`(在PX4源码的mavlink子模块中)添加: ```xml <message id="500" name="MY_GPS"> <field type="uint64_t" name="timestamp">Timestamp (microseconds since system boot)</field> <field type="int32_t" name="lat">Latitude (WGS84), in degrees * 1E7</field> <field type="int32_t" name="lon">Longitude (WGS84), in degrees * 1E7</field> <field type="int32_t" name="alt">Altitude (AMSL), in meters * 1000</field> </message> ``` 然后,在PX4编译时,这个XML会被用来生成头文件。 ### 步骤2:生成消息头 编译PX4,生成的头文件将出现在`build/px4_fmu-v5_default/mavlink/include/mavlink/v2.0`(具体路径根据构建目标而定)。 ### 步骤3:实现发送器 在PX4中,通常我们会在一个模块(比如`mavlink`模块)中发送MAVLink消息。假设我们想发送上面定义的`MY_GPS`消息,我们可以这样做: 在`mavlink_messages.cpp`中的某个函数(比如`mavlink_update`)中: 1. 添加订阅: ```cpp #include <uORB/topics/vehicle_gps_position.h> ... int _gps_sub = orb_subscribe(ORB_ID(vehicle_gps_position)); ``` 2. 在循环中,读取uORB消息,转换为MAVLink消息并发送: ```cpp vehicle_gps_position_s gps; orb_copy(ORB_ID(vehicle_gps_position), _gps_sub, &gps); // 填充MAVLink消息 mavlink_my_gps_t msg_my_gps; msg_my_gps.timestamp = gps.timestamp; msg_my_gps.lat = gps.lat; // 注意单位转换,如果uORB中的单位是度*1e7,则直接赋值 ... // 其他字段 // 发送 mavlink_msg_my_gps_send_struct(_mavlink->get_channel(), &msg_my_gps); ``` 注意:实际中,我们可能不会为每个uORB消息都创建一个新的MAVLink消息,而是尽可能使用已有的标准消息。例如,GPS数据通常使用`GPS_RAW_INT`(ID 24)消息发送。 ### 步骤4:配置默认流式传输 在PX4的`mavlink`模块中,默认的消息流配置在`streams_list`数组(在`mavlink_main.cpp`中)中定义。我们可以添加一个新的条目: ```cpp const StreamListItem streams_list[] = { ... create_stream_list_item("MY_GPS", MAVLINK_MSG_ID_MY_GPS, 1.0f, 0), ... }; ``` 这样,在启动MAVLink实例时,它会默认以1Hz的频率发送`MY_GPS`消息。 或者,通过启动脚本(`rc.mavlink`)使用`mavlink stream`命令设置: ```bash mavlink stream -d 500000 -s MY_GPS -r 10 ``` ### 步骤5:按需流式传输 按需流式传输不需要额外的代码,因为PX4已经实现了`MAV_CMD_SET_MESSAGE_INTERVAL`命令的处理(在`mavlink_receiver.cpp`的`handle_command_message_interval`函数中)。地面站可以发送: ``` MAV_CMD_SET_MESSAGE_INTERVAL: param1: MAVLINK_MSG_ID_MY_GPS(即500) param2: 间隔(微秒),例如100000表示10Hz ``` 这样,PX4就会动态调整该消息的发送速率。 ### 步骤6:接收MAVLink消息(可选) 如果我们还需要接收MAVLink消息(例如,从地面站发送命令来控制无人机),则需要在`mavlink_receiver.cpp`中处理: 1. 在`MavlinkReceiver::handle_message`函数中添加一个case: ```cpp case MAVLINK_MSG_ID_MY_GPS: { mavlink_my_gps_t msg; mavlink_msg_my_gps_decode(&_msg, &msg); // 将msg转换为uORB消息并发布 my_gps_orb_s orb_msg; orb_msg.timestamp = hrt_absolute_time(); orb_msg.lat = msg.lat; ... orb_publish(ORB_ID(my_gps_orb), _my_gps_pub, &orb_msg); break; } ``` 注意:这只是一个示例,实际中可能不需要将MY_GPS消息再传回飞控。 总结:将uORB消息作为MAVLink消息流式传输,主要涉及定义消息(如果需要)、生成头文件、在发送端转换消息并发送、配置流速率(默认和按需)以及可能的接收处理。 下面生成相关问题: </think> ### 如何将uORB消息作为MAVLink消息流式传输 #### 1. **添加MAVLink消息定义** 在PX4开发中,所有MAVLink消息定义位于`PX4-Autopilot/src/modules/mavlink/mavlink/message_definitions/v1.0/`目录: - **新建消息**:在`common.xml`或自定义XML中添加消息结构 ```xml <message id="350" name="ORB_MESSAGE"> <description>Custom uORB to MAVLink bridge</description> <field type="uint64_t" name="timestamp">Timestamp (µs)</field> <field type="float" name="sensor_data">Sensor reading</field> <field type="uint8_t" name="status" enum="STATUS_FLAGS">Status flags</field> </message> ``` - **枚举支持**:添加必要的枚举类型 ```xml <enum name="STATUS_FLAGS"> <entry value="1" name="SENSOR_OK">Sensor functioning</entry> <entry value="2" name="CALIBRATED">Calibration complete</entry> </enum> ``` #### 2. **生成消息头文件** 编译时自动生成消息头文件: ```bash # 生成开发环境头文件 make px4_sitl_default ``` 生成路径:`build/px4_sitl_default/mavlink/include/mavlink/v2.0/` #### 3. **实现消息发送器** 在模块代码中(如`src/modules/mavlink/mavlink_messages.cpp`): ```cpp #include <mavlink/v2.0/common/mavlink_msg_orb_message.h> // 订阅uORB主题 int _orb_sub = orb_subscribe(ORB_ID(vehicle_sensor)); // 发送循环 void Mavlink::send_orb_message() { vehicle_sensor_s sensor_data; if (orb_copy(ORB_ID(vehicle_sensor), _orb_sub, &sensor_data) == PX4_OK) { mavlink_orb_message_t msg; msg.timestamp = sensor_data.timestamp; msg.sensor_data = sensor_data.value; msg.status = (sensor_data.calibrated) ? STATUS_FLAGS_CALIBRATED : 0; mavlink_msg_orb_message_send_struct(_channel, &msg); } } ``` #### 4. **配置默认流式传输** 在`mavlink_main.cpp`中设置默认流速率: ```cpp // 添加至streams_list[] const StreamListItem streams_list[] = { ... {"ORB_MESSAGE", MAVLINK_MSG_ID_ORB_MESSAGE, 10.0f}, // 10Hz默认频率 }; ``` #### 5. **实现按需流式传输** 处理`MAV_CMD_SET_MESSAGE_INTERVAL`命令: ```cpp // mavlink_receiver.cpp case MAVLINK_MSG_ID_COMMAND_LONG: if (cmd_msg.command == MAV_CMD_SET_MESSAGE_INTERVAL) { uint16_t msg_id = static_cast<uint16_t>(cmd_msg.param1); if (msg_id == MAVLINK_MSG_ID_ORB_MESSAGE) { // 设置新速率(µs间隔) configure_stream("ORB_MESSAGE", 1e6f / cmd_msg.param2); } } break; ``` #### 6. **实时调试与验证** - **查看流状态**: ```bash mavlink status # 输出:ORB_MESSAGE: rate=10.0 B/s ``` - **动态调整速率**: ```bash mavlink stream -u 14556 -s ORB_MESSAGE -r 50 # 设置50Hz ``` - **QGC MAVLink Inspector**: 1. 在QGC的`Analyze Tools > MAVLink Inspector`中查看实时数据 2. 验证字段映射是否正确 #### 7. **性能优化技巧** - **数据对齐**:确保结构体字段对齐 ```cpp __attribute__((packed)) struct vehicle_sensor_s {...}; ``` - **频率控制**:使用环形缓存避免高频uORB消息阻塞 ```cpp orb_set_interval(_orb_sub, 20); // 限制订阅更新率为50Hz ``` - **差分传输**:仅当数据变化时发送 ```cpp if (fabsf(sensor_data.value - _last_value) > 0.01f) { send_message(); _last_value = sensor_data.value; } ``` ---
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