HDL bits----arithmetic circuits

1.hadd

module top_module( 
    input a, b,
    output cout, sum );
    assign sum=(a^b)^0;
    assign cout=(a&b)|((a^b)&0);
endmodule

2.fadd

module top_module( 
    input a, b, cin,
    output cout, sum );
    assign sum=(a^b)^cin;
    assign cout=(a&b)|((a^b)&cin);
endmodule

3.adder3

module top_module( 
    input [2:0] a, b,
    input cin,
    output [2:0] cout,
    output [2:0] sum );
    assign sum[0]=(a[0]^b[0])^cin;
    assign cout[0]=(a[0]&b[0])|(a[0]^b[0])&cin;
    assign sum[1]=(a[1]^b[1])^cout[0];
    assign cout[1]=(a[1]&b[1])|(a[1]^b[1])&cout[0];
    assign sum[2]=(a[2]^b[2])^cout[1];
    assign cout[2]=(a[2]&b[2])|(a[2]^b[2])&cout[1];
   
    
endmodule

4.Exams/m2014 q4j

（我写的）

module top_module (
    input [3:0] x,
    input [3:0] y, 
    output [4:0] sum);
    wire w1,w2,w3;
    assign sum[0]=(x[0]^y[0])^0;
    assign w1=(x[0]&y[0])|(x[0]^y[0])&0;
    assign sum[1]=(x[1]^y[1])^w1;
    assign w2=(x[1]&y[1])|(x[1]^y[1])&w1;
    assign sum[2]=(x[2]^y[2])^w2;
    assign w3=(x[2]&y[2])|(x[2]^y[2])&w2;
    assign sum[3]=(x[3]^y[3])^w3;
    assign sum[4]=(x[3]&y[3])|(x[3]^y[3])&w3;
endmodule

module top_module (
	input [3:0] x,
	input [3:0] y,
	output [4:0] sum
);

	// This circuit is a 4-bit ripple-carry adder with carry-out.
	assign sum = x+y;	// Verilog addition automatically produces the carry-out bit.

	// Verilog quirk: Even though the value of (x+y) includes the carry-out, (x+y) is still considered to be a 4-bit number (The max width of the two operands).
	// This is correct:
	// assign sum = (x+y);
	// But this is incorrect:
	// assign sum = {x+y};	// Concatenation operator: This discards the carry-out
endmodule

（上图 官网的）

5.Exams/ece241 2014 q1c

module top_module (
    input [7:0] a,
    input [7:0] b,
    output [7:0] s,
    output overflow
); //
    assign overflow=(~a[7]&(~b[7])&s[7])|(a[7]&b[7]&(~s[7]));
    assign s=a+b;
    // assign s = ...
    // assign overflow = ...

endmodule

6.adder100

(我靠）

module top_module( 
    input [99:0] a, b,
    input cin,
    output cout,
    output [99:0] sum );
    
    assign {cout,sum}=a+b+cin;
endmodule

7.bcdadd4

module top_module ( 
    input [15:0] a, b,
    input cin,
    output cout,
    output [15:0] sum );
    wire [3:0] wa;
    wire [3:0] wb;
    wire [3:0] wc;
    wire [3:0] wd;
    wire w1,w2,w3,w4;
        bcd_fadd instance1(.a(a[3:0]),.b(b[3:0]),.cin(cin),.cout(w1),.sum(wa));
        bcd_fadd instance2(.a(a[7:4]),.b(b[7:4]),.cin(w1),.cout(w2),.sum(wb));
        bcd_fadd instance3(.a(a[11:8]),.b(b[11:8]),.cin(w2),.cout(w3),.sum(wc));
        bcd_fadd instance4(.a(a[15:12]),.b(b[15:12]),.cin(w3),.cout(w4),.sum(wd));
    assign sum={wd,wc,wb,wa};
    assign cout=w4;
endmodule