fpga prototyping note1

guidelines

Using HPM, Tom, the project architect, has created five ‘subprojects’ that comprise the target design, and assigned them to four engineers – Ivan owns one sub project that applies to two instances of the same module.

Each project can be worked on independently and in parallel and there is ample flexibility available when the architect decides where to set the boundaries, and what format they take.

For example, a subproject can be either instance- or module-based. Subprojects can also be either ‘top-down’, passing the post-compile RTL netlist result (SRS) consisting of generic technology-independent primitives up to the top-level project; or they can be ‘bottom-up’, passing the final post-map gate-level netlist (EDIF) consisting of technology specific primitives up to the top level project.

The advantages here go beyond the divisions. Each subproject holder can use various tools that allow for incremental development using both express features (e.g. Fast Compile) and others that require reiterations that only cover an altered portion (e.g. Compile Points).

 

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