fairy0905的专栏

上电复位  硬件热复位 软件热复位  软件局部复位 内核热复位 低功耗复位  watchdog复位  两级CG:CG1: 可将节点工作时钟完全关断；CG2: 低功耗控制，对工作时钟进行实时动态频率调整MUX1: 选择调试时钟或者测试时钟MUX2:选择工作时钟或者MUX1输出...

High Reuse  

所谓给综合加时序约束就是说要给综合器一个要求，比如我要求某条时序路径的最大延迟不能超过5ns，那么我可以用如下命令进行约束：set_max_delay 5 -from {路径起点} -to {路径终点}　　那么综合器收到这条指令之后，它会尽它所能去综合出延迟小于5ns的电路，如果它的最终结果为1ns，那么意味着电路的时序满足要求，否则，不...

Both the Normal Place & Route and Incremental Place & Route might include physicaloptimization.floorplanning:https://www.xilinx.com/video/hardware/design-analysis-floo...

If you have a shared area of memory used for passing control information between masters (or processes running on a master), you want to make sure that you complete the READ/WRITE sequence without ano...

http://xilinx.eepw.com.cn/news/list/t/10http://xilinx.eepw.com.cn/news/article/a/1476http://www.cnblogs.com/linjie-swust/archive/2012/03/01/FPGA.htmlhttps://www.cnblogs.com/freshair_cnblog/archi...

HPM-hierarchical project management在HK平台利用compile point  时，hds 没有问题，但是mdu 不管采用hard 还是soft syn后都会出现combined clock convertion  不全的问题。这跟模块设计有关。incrementalcompile point -used to implement incrementa...

Manipulating DRCS禁用不定态传播vivado  -mode tcl -source hk_prj.tcl -tclargs --origin_dir  ...

guidelinesUsing HPM, Tom, the project architect, has created five ‘subprojects’ that comprise the target design, and assigned them t...

        

Port Ordering  Use FunctionUse Loops and Arrays (1)Use Loops and Arrays (2)Do Not Use Hard-Coded Numeric ValueAvoid Clock Buffers Avoid Using Internally Generated Clocks Ga...

Guideline: If PLL is used, then some means of disabling or bypassing the PLL should be provided. Makes chip testing and debug much easier .Reset Rule: The basic reset strategy must be documented. ...

DMA操作     DMA 为其运行使用 3态 FSM（有限状态机），相关描述如下面三个阶段：状态1. 作为一个初始状态，DMA等待DMA 请求。一旦请求到达则跳到状态 2。在此状态下DMA ACK和 INT REQ 为 0。状态2. 在此状态，DMA ACK变为 1而且计数器（CURR_TC）从DCON[19:0]寄存器中加载。注意 DMA ACK 保 持为1 直到之后将其清除。...

http://www.eetop.cn/blog/html/28/1561828-5940195.htmlhttp://www.eetop.cn/blog/html/28/1561828-6333555.htmlhttps://www.doulos.com/knowhow/sysverilog/uvm/easier_uvm_guidelines/detail/MentorGraphic...