视频剖析-Video Timing

本文解释了视频显示的基本原理,介绍了视频看起来是连续动态的原因,并详细解析了视频Timing的概念及其作用,包括垂直同步和水平同步信号的工作机制。

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大家应该都知道,视频看起来是持续动态的,但是实际上是由一系列的静态画面,在很短的时间内更替,在人眼上就产生视觉残留,以至于你的眼睛感觉是动态画面。大家看到的视频中大多数是每秒闪过50~60幅画面,对于电脑画面大概是每秒闪过70~80幅画面。

要说timing是什么,先说下一般的图像是怎么显示在屏幕上的。

视频源发出的一幅幅的画面,送到屏幕后,屏幕将每一幅画面从上到下逐行的扫描每个像素显示在屏幕上,不间断的重复,直到一段视频数据结束。

而视频数据是连续的,怎么就知道哪段数据是显示一个画面?

怎么知道一个画面中哪一段数据又是显示这一行的?

Timing 就是解决这两问题的。

Video timing 包含两个信号:水平同步Hs(horizontal sync)和垂直同步Vs(vertical sync)
Vertical sync -->用来标识什么时候开始送出一幅新画面
Horizontal sync -->用来标识什么时候开始新一行的图像扫描

Vertical sync 和 Horizontal sync 信号有三种传送方式:
1、单独传送vertical sync 和 Horizontal sync两路信号,如电脑上用的VGA信号,HDMI高清数字视频信号;
2、将vertical sync和horizontal sync信号复合在一路单独传送,如S-Video型号(其timing信号时复合在其Y信号中);
3、将vertical sync和horizontal sync复合在一起的信号又再复合进视频信号中一起传送,如CVBS信号;

举个例子说明timing中包含了哪些信息:
如一个视频信号timing为(1024*768@60),1024*768表示是SVGA分辨率(其中1024表示一幅图像的列数,因每一个象素点有R/G/B三点组成,故共有1024*3列;768表示一幅图像的行数,共768行),60Hz表示的就是vertical sync(即每一个画面的显示时间为1/60s=16.67ms),由于每一幅画面要扫描768行,所以每一行的扫描时间即为16.67ms/768=21.7us,即可得出horizontal sync。

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最新发布
07-13
### Video Timing Controller in IT Context In the context of IT, particularly within embedded systems and FPGA-based designs, a **Video Timing Controller (VTC)** is an essential IP core used to manage and synchronize video signals. The VTC generates timing signals required for video output, such as horizontal sync, vertical sync, and pixel clocks, ensuring that the video data aligns with the display's refresh rate and resolution requirements[^1]. The VTC operates by defining a set of timing parameters that correspond to specific video standards or custom resolutions. These parameters include horizontal and vertical active pixel counts, front porch, back porch, sync pulse widths, and total pixel and line counts. Once configured, the VTC provides the necessary synchronization signals for driving displays or interfacing with other video processing blocks. When integrating a Video Timing Controller into a design, it is typically added via a Block Design interface in tools like Xilinx Vivado. This process involves searching for the "video timing" keyword and selecting the appropriate IP core to add it to the design environment[^1]. Afterward, the VTC must be configured with the desired video mode or custom timing parameters to match the target display's specifications. #### Key Features of Video Timing Controller - **Synchronization Signals**: Provides horizontal and vertical synchronization pulses along with pixel clocks. - **Resolution Support**: Supports standard video resolutions (e.g., 720p, 1080p) and custom configurations. - **Interface Compatibility**: Compatible with AXI4-Stream interfaces for seamless integration with video processing pipelines[^1]. - **Flexible Configuration**: Allows users to define custom video modes through parameter settings. Below is an example of configuring a Video Timing Controller in Xilinx Vivado using Tcl scripting: ```tcl # Create a new Video Timing Controller instance create_ip -name v_tc -vendor xilinx.com -library ip -module_name v_tc_0 # Set the video mode to 640x480@60Hz set_property -dict [list CONFIG.video_mode {640x480p60}] [get_ips v_tc_0] # Generate the output products generate_target all [get_files [get_property NAME [get_ips v_tc_0]]] ``` This script demonstrates how to instantiate and configure a Video Timing Controller for a specific video mode using Tcl commands in Vivado[^1]. ###
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