Verilog编程巩固

在线练习

在线上Verilog编程网站学习。从门电路、组合电路、时序电路中各选3个以上的例题实践完成。
在线练习网站.

实践记录

1.门电路

1.1与门

module top_module( 
    input a, 
    input b, 
    output out );
	assign out=a&b;
endmodule

1.2非门

module top_module( input in, output out );
	assign out=~in;
endmodule

1.3或非门

module top_module( 
    input a, 
    input b, 
    output out );
	assign out=~(a|b);
endmodule

2.组合电路

2.1半加器

module top_module( 
    input a, b,
    output cout, sum );
assign cout=a&b;
assign sum=a^b;
endmodule

2.2全加器

module top_module( 
    input a, b, cin,
    output cout, sum );
    assign{cout,sum} = a + b + cin;
endmodule

2.3二选一多路复用器

module top_module( 
    input a, b, sel,
    output out ); 
    assign out=(sel)?b:a;
endmodule

3.时序逻辑

3.1D触发器

2.编写代码
module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//

    // Use a clocked always block
    //   copy d to q at every positive edge of clk
    //   Clocked always blocks should use non-blocking assignments
    always@(posedge clk) begin
        q <= d;
    end

endmodule

3.21到12计数器

module top_module (
    input clk,
    input reset,
    input enable,
    output [3:0] Q,
    output c_enable,
    output c_load,
    output [3:0] c_d
); //

    count4 the_counter (clk, c_enable, c_load, c_d /*, ... */ );
    reg [3:0] temp;

    //4-bit计数器的控制信号
    assign c_enable = enable;
    //带复位和置位，
    assign c_load   = reset | (Q == 4'd12 & enable == 1'b1);
    assign c_d      = 4'b1;

//    count4 the_counter (clk, c_enable, c_load, c_d, Q );
    count4 Inst_count4
    (
        .clk(clk),
        .enable(c_enable),
        .load(c_load),
        .d(c_d),
        .Q(Q)
    );
endmodule

3.3带复位按钮的D触发器

module top_module (
    input clk,
    input reset,            // Synchronous reset
    input [7:0] d,
    output [7:0] q
);
always@(posedge clk) begin
        if(reset)
            q <= 8'b0;
        else
    	    q <= d;
    end
endmodule