parameter idle = 2'd0;
parameter st1 = 2'd1;
parameter st2 = 2'd2;
reg [1:0] cur_state;
always@(posedge clk_i or negedge rst_n ) begin
if(!rst_n)
cur_state <= idle;
else
cur_state <= next_state;
end
reg [1:0] next_state;
always@ (*) begin
case (cur_state)
idle :
if(vs_i == 0)
next_state = st1;
else
next_state = idle;
st1 :
if(vs_i == 1)
next_state = st2;
else
next_state = st1;
st2:
if(vs_i == 0)
next_state = idle;
else
next_state = idle;
default:
next_state = idle;
endcase
end
reg flag;
always@(posedge clk_i or negedge rst_n ) begin
if(!rst_n)
flag <= 0;
else if(cur_state == st2 && vs_i == 0)
flag <= 1;
else
flag <= 0;
end
其他序列检测可参照例程实现