组合逻辑之3-8 译码器利用Verilog实现

横二彪

已于 2022-10-13 17:40:43 修改

阅读量1.8k

点赞数

分类专栏： FPGA 文章标签： fpga verilog

于 2021-03-17 21:29:18 首次发布

本文链接：https://blog.youkuaiyun.com/dalingertong/article/details/114950926

版权

FPGA 专栏收录该内容

26 篇文章

订阅专栏

组合逻辑之3-8 译码器利用Verilog实现

module demo(a,b,c,out);
	input a;
	input b;
	input c;
	
	output reg[7:0]out;
	
	always@(a,b,c) begin
		case({a,b,c})
			3'b000: out = 8'b0000_0001;
			3'b001: out = 8'b0000_0010;
			3'b010: out = 8'b0000_0100;
			3'b011: out = 8'b0000_1000;
			3'b100: out = 8'b0001_0000;
			3'b101: out = 8'b0010_0000;
			3'b110: out = 8'b0100_0000;
			3'b111: out = 8'b1000_0000;
		endcase
	end
endmodule

TestBanch

`timescale 1ns/1ns

module demo_tb;

	reg a;
	reg b;
	reg c;
	
	wire [7:0]out;
	
	demo demo(     //待测试文件例化到仿真文件
			.a(a),
			.b(b),
			.c(c),
			.out(out)
			);
	initial begin 
		a = 0;b = 0;c = 0;
		#200
		a = 0;b = 0;c = 1;
		#200
		a = 0;b = 1;c = 0;
		#200
		a = 0;b = 1;c = 1;
		#200
		a = 1;b = 0;c = 0;
		#200
		a = 1;b = 0;c = 1;
		#200
		a = 1;b = 1;c = 0;
		#200
		a = 1;b = 1;c = 1;
		#200
		$stop;
	end
endmodule