计算机组成实验-第3章-Datapath基本组件设计

1.程序计数器

module pc_top(clk, rst,i_pc,o_pc );

    input wire clk, rst;

    output wire [8:0] i_pc;

    output wire [8:0] o_pc;

    single_pc        M1(clk,rst,i_pc,o_pc);

    single_pc_plus4 M2(o_pc, i_pc);

endmodule

 

module single_pc(clk, rst, i_pc, o_pc);

    input wire clk, rst;

    input wire [8:0] i_pc;

    output reg [8:0] o_pc=0;

    always @(posedge clk)

         o_pc= rst ? 9'b11111111: i_pc;

// o_pc= rst ? {9{1’b1}}: i_pc;

endmodule

 

module single_pc_plus4(i_pc, o_pc);

    input  wire [8:0] i_pc;

    output wire [8:0] o_pc;

    assign o_pc = i_pc[8:0] + 1;

endmodule

 

//模拟测试程序

module test;

    // Inputs

    reg clk;

    reg rst;

    reg [8:0] i_pc;

    // Outputs

    wire [8:0] o_pc;

    // Instantiate the Unit Under Test (UUT)

    single_pc uut (

        .clk(clk),

        .rst(rst),

        .i_pc(i_pc),

        .o_pc(o_pc)

    );

 

    initial begin

        // Initialize Inputs

        clk = 0;

        rst = 0;

        i_pc = 0;

        // Wait 100 ns for global reset to finish

        #100;

      clk=~clk;

        // Add stimulus here

    end

endmodule

 

2．32位加法器的Verilog实现

module single_add (i_op1,i_op2,o_out);

    parameter N = 32;

    input  wire[N-1:0] i_op1, i_op2;

    output wire[N-1:0] o_out;

    assign o_out = i_op1 + i_op2;

endmodule

module add_test;

    // Inputs

    reg [31:0] i_op1;

    reg [31:0] i_op2;

    // Outputs

    wire [31:0] o_out;

    // Instantiate the Unit Under Test (UUT)

    single_add uut (

        .i_op1(i_op1),

        .i_op2(i_op2),

        .o_out(o_out)

    );

    initial begin

        i_op1 = 0;

        i_op2 = 0;

        // Wait 100 ns for global reset to finish

        #100;

      i_op1=0;

        i_op2=0;

        #100;

        i_op1=0;

        i_op2=1;

        #100;

        i_op1=1;

        i_op2=0;

        #100;

        i_op1=1;

        i_op2=1;

        #100;

        i_op1=11000;

        i_op2=10011;

        #100;

        i_op1=00010;

        i_op2=01110;

        // Add stimulus here

    end

endmodule

 

3．多路选择器（4位2选1选择器）

module single_mux(Ai, Bi, sel, out);

    input [3:0] Ai;

    input [3:0] Bi;

    input sel;

    output [3:0] out;

    assign out[3:0]=(sel==1)?(Bi[3:0]):(Ai[3:0]);

endmodule

 

4．符号位扩展

module single_signext(i_16, o_32);

    input wire [15:0] i_16;

    output reg [31:0] o_32;

    always @(i_16)

        o_32 <= {{16{i_16[15]}}, i_16[15:0]};

endmodule

模拟程序

module sign_test;

    // Inputs

    reg [15:0] i_16;

    // Outputs

    wire [31:0] o_32;

    // Instantiate the Unit Under Test (UUT)

    single_signext uut (

        .i_16(i_16),

        .o_32(o_32)

    );

 

    initial begin

        // Initialize Inputs

        i_16 = 0;

        // Wait 100 ns for global reset to finish

            #100;

        i_16 = 16'b0000000000000001;

            #100;

        i_16 = 16'b0000000000000010;

            #100;

        i_16 = 16'b0000000000000011;

            #100;

        i_16 = 16'b0000000000000100;

           #100;

        i_16 = 16'b0000001000000100;

            #100;

        i_16 = 16'b1000000000000100;

            #100;

        i_16 = 16'b1000000001000100;

            #100;

        i_16 = 16'b1000000010000100;

           #100;

        i_16 = 16'b1000000010000101;

         

        // Add stimulus here

    end

endmodule

 

 

5.四位2选1程序

5.1主程序

module top(clk,switch, led, segment, digit_anode);

    input  wire       clk;

    //input  wire  button;

    input  wire [8:0] switch;

    output wire [7:0] led;

    output wire [7:0] segment;

    output wire  [3:0] digit_anode;

             reg [3:0] disp_num;

             wire  button_out;

             wire [3:0] S;

 

    single_mux   I1(switch[3:0], switch[7:4], switch[8], S);

    display      I4(clk,{12'h000,S},digit_anode,segment);

    assign  led = switch;  

endmodule

 

 

 

 

 

5.2四位2选1程序

module single_mux (A, B, C, S);

 

        parameter N = 4;           

        input  wire [N-1:0] A, B;

        input  wire         C;

        output wire [N-1:0] S;

       

        assign S = C ? B : A ;

       

endmodule

5.3显示程序

module display(clk,disp_num,digit_anode,segment);

    input                       clk;   

    input       [15:0]          disp_num;

    output      [3:0]           digit_anode;   

    output      [7:0]           segment;

 

    reg         [3:0]           digit_anode;   

    reg         [7:0]           segment;

    reg         [11:0]          count = 0;

    wire        [15:0]          disp_num;

    reg         [3:0]           num;

 

    always @(posedge clk) begin

        case (count[11:10])

            2'b00 : begin

                digit_anode <= 4'b1110;                     //1st element

                num <= disp_num[3:0];

         end

            2'b01 : begin

                digit_anode <= 4'b1101;                 //2nd element

                num <= disp_num[7:4];

             end

            2'b10 : begin

                digit_anode <= 4'b1011;                 //3rd element

                num <= disp_num[11:8];

              end

            2'b11 : begin

                digit_anode <= 4'b0111;                 //4th element

                num <= disp_num[15:12];

             end

        endcase

 

        case (num)

            4'b0000: segment <= 8'b11000000;

            4'b0001: segment <= 8'b11111001;

            4'b0010: segment <= 8'b10100100;

            4'b0011: segment <= 8'b10110000;

            4'b0100: segment <= 8'b10011001;

            4'b0101: segment <= 8'b10010010;

            4'b0110: segment <= 8'b10000010;

            4'b0111: segment <= 8'b11111000;

            4'b1000: segment <= 8'b10000000;

            4'b1001: segment <= 8'b10010000;

            4'b1010: segment <= 8'b10001000;

            4'b1011: segment <= 8'b10000011;

            4'b1100: segment <= 8'b11000110;

            4'b1101: segment <= 8'b10100001;

            4'b1110: segment <= 8'b10000110;

            4'b1111: segment <= 8'b10001110;

            default: segment <= 8'b00000000;

        endcase

    end

 

    always @(posedge clk)begin

        count <= count + 1;

    end

endmodule

5.4约束文件

NET "clk" LOC = "T9";

//NET "button" LOC = "M13";

NET "digit_anode[0]" LOC = "D14";

NET "digit_anode[1]" LOC = "G14";

NET "digit_anode[2]" LOC = "F14";

NET "digit_anode[3]" LOC = "E13";

 

NET "segment[0]" LOC = "E14";

NET "segment[1]" LOC = "G13";

NET "segment[2]" LOC = "N15";

NET "segment[3]" LOC = "P15";

NET "segment[4]" LOC = "R16";

NET "segment[5]" LOC = "F13";

NET "segment[6]" LOC = "N16";

NET "segment[7]" LOC = "P16";

 

NET "switch[0]" LOC = "F12";

NET "switch[1]" LOC = "G12";

NET "switch[2]" LOC = "H14";

NET "switch[3]" LOC = "H13";

NET "switch[4]" LOC = "J14";

NET "switch[5]" LOC = "J13";

NET "switch[6]" LOC = "K14";

NET "switch[7]" LOC = "K13";

NET "switch[8]" LOC = "M10";

 

NET "led[0]" LOC = "K12";

NET "led[1]" LOC = "P14";

NET "led[2]" LOC = "L12";

NET "led[3]" LOC = "N14";

NET "led[4]" LOC = "P13";

NET "led[5]" LOC = "N12";

NET "led[6]" LOC = "P12";

NET "led[7]" LOC = "P11";