向axis-fifo写入数据的方法

最新推荐文章于 2025-05-10 13:00:00 发布

原创

最新推荐文章于 2025-05-10 13:00:00 发布 · 723 阅读

11 ·

CC 4.0 BY-SA版权

文章标签：

#fpga开发

这篇文章详细描述了一个模块DMA帧生成器的设计，使用状态机控制数据传输，包括输入信号如trans_start、时钟(clk)以及AXI-Stream接口的输出(m_axis_tdata,m_axis_tlast,m_axis_tvalid)。它通过状态转移来管理传输计数(trans_cnt)和数据打包(r_tdata)过程。

module dma_frame_gen #(
    parameter TRANS_NUM = 32'd1550336 //1514*1024
    )
    (
    input resetn,
    input clk,
    input trans_start,
    // axi-stream
    output [31:0] m_axis_tdata,
    output [3:0] m_axis_tkeep,
    output m_axis_tlast,
    output m_axis_tvalid,
    input m_axis_tready
    );
    
assign m_axis_tkeep = 4'b1111;
reg trans_start_0, trans_start_1;
wire pos_trans_start;
assign pos_trans_start = trans_start_0 & (~trans_start_1);
always @(posedge clk or negedge resetn) begin
    if(~resetn) begin
        trans_start_0 <= 1'd0;
        trans_start_1 <= 1'd0;
    end
    else begin
        trans_start_0 <= trans_start;
        trans_start_1 <= trans_start_0;
    end
end
localparam IDLE = 2'b00;
localparam TRANS = 2'b01;
localparam DONE = 2'b10;
reg [1:0] state;
reg [31:0] trans_cnt;
reg [31:0] r_tdata;
reg r_tvalid, r_tlast;
always @(posedge clk or negedge resetn) begin
    if(!resetn) begin
        state <= IDLE;
        r_tdata <=