AresDing的专栏

==================================================================== start.s Vector_Table: [0x00] B Reset_GO; [0x04] LDR PC, Undefined_Addr; [0x08] LDR PC, SWI_Addr; [0x0C] LDR PC, Prefetch_Addr...

the clock controller generates all clocks for vedio, audio, cpu, amba and all engine modules, nuc970 include two PLL Modules; the clock souce for each module come from the PLL, or from external cryst...