QEMU ARM interrupt system architecture 2

I'd like to list the log here to help the understand of the process.

GPIO_IN initialize API is :

void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n)
{
    qdev_init_gpio_in_named(dev, handler, NULL, n);
}

static inline void qdev_init_gpio_in_named(DeviceState *dev,
                                           qemu_irq_handler handler,
                                           const char *name, int n)
{
    qdev_init_gpio_in_named_with_opaque(dev, handler, dev, name, n);
}

void qdev_init_gpio_in_named_with_opaque(DeviceState *dev,
                                         qemu_irq_handler handler,
                                         void *opaque,
                                         const char *name, int n)
{
    int i;
    NamedGPIOList *gpio_list = qdev_get_named_gpio_list(dev, name);

    assert(gpio_list->num_out == 0 || !name);
    gpio_list->in = qemu_extend_irqs(gpio_list->in, gpio_list->num_in, handler,
                                     opaque, n);
    .....
    gpio_list->num_in += n;
}

qemu_irq *qemu_extend_irqs(qemu_irq *old, int n_old, qemu_irq_handler handler,
                           void *opaque, int n)
{
    qemu_irq *s;
    int i;

    if (!old) {
        n_old = 0;
    }
    s = old ? g_renew(qemu_irq, old, n + n_old) : g_new(qemu_irq, n);
    for (i = n_old; i < n + n_old; i++) {
        s[i] = qemu_allocate_irq(handler, opaque, i);
    }
    return s;
}

qemu_irq qemu_allocate_irq(qemu_irq_handler handler, void *opaque, int n)
{
    struct IRQState *irq;
    
    irq = IRQ(object_new(TYPE_IRQ));
    irq->handler = handler;
    irq->opaque = opaque;
    irq->n = n;
    printf("alexdebug:%s irq at %p, n is %d\n",__func__,irq,n);
    return irq;
}

1. ARM CORE GPIO_IN irq creation.

static void arm_cpu_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    .....
    qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
    .....
}

The log is:

alexdebug:qemu_allocate_irq irq at 0x7fffbe6b4480, n is 0
alexdebug:qemu_allocate_irq irq at 0x7fffbe6644c0, n is 1
alexdebug:qemu_allocate_irq irq at 0x7fffbe6702c0, n is 2
alexdebug:qemu_allocate_irq irq at 0x7fffbe66fbe0, n is 3

2. GIC GPIO_IN irq creation

static void arm_gic_realize(DeviceState *dev, Error **errp)
{
    GICState *s = ARM_GIC(dev);
    .....
    gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops, gic_virt_ops);
    .....
}

void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
                            const MemoryRegionOps *ops,
                            const MemoryRegionOps *virt_ops)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(s);
    int i = s->num_irq - GIC_INTERNAL;

    /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
     * GPIO array layout is thus:
     *  [0..N-1] SPIs
     *  [N..N+31] PPIs for CPU 0
     *  [N+32..N+63] PPIs for CPU 1
     *   ...
     */
    i += (GIC_INTERNAL * s->num_cpu);
    qdev_init_gpio_in(DEVICE(s), handler, i);

    for (i = 0; i < s->num_cpu; i++) {
        sysbus_init_irq(sbd, &s->parent_irq[i]);
    }
    for (i = 0; i < s->num_cpu; i++) {
        sysbus_init_irq(sbd, &s->parent_fiq[i]);
    }
    for (i = 0; i < s->num_cpu; i++) {
        sysbus_init_irq(sbd, &s->parent_virq[i]);
    }
    for (i = 0; i < s->num_cpu; i++) {
        sysbus_init_irq(sbd, &s->parent_vfiq[i]);
    }
    .....
}

The log is:

alexdebug:arm_gic_realize
alexdebug:arm_gic_common_realize begin, SysBusDevice is at 0x7fffbe7a9ce0
alexdebug:qemu_allocate_irq irq at 0x7fffbe6627b0, n is 0
alexdebug:qemu_allocate_irq irq at 0x7fffbe662900, n is 1
alexdebug:qemu_a