【ZYNQ-7000开发之七】AXI CDMA特点以及在PS端使用的步骤_理论部分未完待续

最新推荐文章于 2025-05-07 14:00:00 发布

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最新推荐文章于 2025-05-07 14:00:00 发布

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分类专栏： Zynq AXI 嵌入式文章标签： AXI-CDMA ZYNQ 嵌入式系统

本文链接：https://blog.youkuaiyun.com/RZJMPB/article/details/50376041

本文详细介绍了ZYNQ-7000 SoC中AXI CDMA的功能特性，包括独立的AXI4-Lite接口、固定32位数据宽度、 Scatter/Gather模式等。AXI CDMA提供高性能DMA，支持Simple DMA和Scatter Gather自动化模式。在PS端配置中，讲解了Simple DMA和Scatter Gather模式的步骤，以及中断和寄存器设置。

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本编文章是AXI Central Direct Memory Access v4.1的阅读笔记

硬件规格部分

简介:

AXI CDMA为嵌入式系统提供了高性能的片上互联
The AXI CDMA provides high-bandwidth Direct Memory Access (DMA) between a memory-mapped source address and a memory-mapped destination address using the AXI4 protocol. An optional Scatter
Gather (SG) feature can be used to offload control and sequencing tasks from thesystem CPU.
初始化，状态和控制寄存器都是通过AXI4-Lite slave接口控制

特点概要

Independent AXI4-Lite slave interface for register access
- Fixed 32-bit data width
- Optional asynchronous operation mode
Independent AXI4 Master interface for the primary CDMA datapath. Parameterizable width of 32, 64, 128, 256, 512, and 1,024 bits with fixed-address burst (key hole) support.
Independent AXI4 Master interface for optional Scatter/Gather function. Fixed 32-bit data width.
Optional Data Realignment Engine for the primary CDMA datapath. Available with 32
and 64-bit datapath widths.
Provides Simple DMA only mode and an optional hybrid mode supporting both Simple
DMA and Scatter Gather automation.
Support for up to 64-bit Address Space

模式：

Register Direct Mode

吞吐量一般，使用简单，占用的逻辑资源少一些。

Scatter/Gather Mode

高吞吐量，减少CPU的干预，释放CPU。使用要复杂一些，也更加消耗逻辑资源。

AXI CDMA的结构框图

DataMover

The DataMover is used for high-throughput transfer of data. The DataMover provides CDMA operations with 4 KB address boundary protection, automatic burst partitioning, and can queue multiple transfer requests. Furthermore, the DataMover provides byte-level data realignment (for 32-bit and 64-bit data widths) allowing the CDMA to read from and write to any byte offset combination.

Unaligned Transfers

The AXI DataMover core optionally supports the Data Realignment Engine (DRE). When the DRE is enabled, data is realigned to the byte (8 bits) level on the Memory Map datapath (32-bit,64-bit).
If the DRE is enabled, data reads can start from any Address byte offset. Similarly, when the DRE is enabled, the writes can happen at any byte offset address. For example, if Memory Map Data Width = 32, data is aligned if it is located at address offsets of 0x0, 0x4, 0x8, 0xC, etc. Data is unaligned if it is located at address offsets of 0x1, 0x2, 0x3 and so forth.
Note: Performing unaligned transfers when DRE is disabled will give unpredictable results
执行不对齐传输会出现不可预测的结果，那这种方式的优势是什么？