CPU设计实战 lab3

Lab3

题目说Lab3有七处错误，我怀疑Mistake 5或者Mistake 8是原本就有的，作者没发现的问题

Mistake 1

Run Simulation后发现debug_wb_pc的值一直为XXXXXXXX,向前溯源可以发现原因出在了ID_stage中，未对ds_valid进行赋值，然后一直影响到debug_wb_pc的值

修改前:

always @(posedge clk) begin
    if (fs_to_ds_valid && ds_allowin) begin
        fs_to_ds_bus_r <= fs_to_ds_bus;
    end
end

修改后代码:

always @(posedge clk) begin
    if (reset) begin
        ds_valid <= 1'b0;
    end
    else if (ds_allowin) begin
        ds_valid <= fs_to_ds_valid;
    end

    if (fs_to_ds_valid && ds_allowin) begin
        fs_to_ds_bus_r <= fs_to_ds_bus;
    end
end

Mistake 2