HDLbits Verification: Reading Simulations

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#verilog

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这篇博客聚焦于Verilog代码的错误检测，包括MUX、AND门、加减运算器和CASE结构的错误，并提供了修复方案。同时介绍了从模拟波形构建电路的过程，涉及逻辑门及组合逻辑电路的设计。文章强调了代码正确性和电路功能验证的重要性。

Verification: Reading Simulations

Finding bugs in code

Bugs mux2

module top_module (
    input sel,
    input [7:0] a,
    input [7:0] b,
    output [7:0] out  );

    assign out = sel ? a : b;

endmodule

Bugs nand3

module top_module (input a, input b, input c, output out);//
    wire out1;
    andgate inst1 ( out1,a,b,c,1'b1,1'b1 );
    assign out = ~out1;
endmodule

Bugs mux4

module top_module (
    input [1:0] sel,
    input [7:0] a,
    input [7:0] b,
    input [7:0] c,
    input [7:0] d,
    output [7:0] out  ); //

    wire [7:0] muxA, muxB;
    mux2 mux0 ( sel[0],    a,    b, muxA );
    mux2 mux1 ( sel[0],    c,    d, muxB );
    mux2 mux2 ( sel[1], muxA, muxB,  out );

endmodule

Bugs addsubz

// synthesis verilog_input_version verilog_2001
module top_module ( 
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);//

    always @(*) begin
        case (do_sub)
          0: out = a+b;
          1: out = a-b;
        endcase

        if (out == 8'd0)
            result_is_zero = 1;
        else
            result_is_zero = 0;
    end

endmodule

Bugs case

module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid );//

     always @(*)
     begin
     out = 0;
     valid=1;
        case (code)
            8'h45: out = 0;
            8'h16: out = 1;
            8'h1e: out = 2;
            8'h26: out = 3;
            8'h25: out = 4;
            8'h2e: out = 5;
            8'h36: out = 6;
            8'h3d: out = 7;
            8'h3e: out = 8;
            8'h46: out = 9;
            default: valid = 0;
        endcase
     end
endmodule

Building a circuit from a simulation waveform

circuit1

module top_module (
    input a,
    input b,
    output q );//

    assign q = a & b; // Fix me

endmodule

circuit2

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//

    assign q = ~a&~b&~c&~d | a&b&~c&~d | ~a&b&~c&d | a&~b&~c&d | ~a&~b&c&d | a&b&c&d | ~a&b&c&~d | a&~b&c&~d; // Fix me

endmodule

circuit3

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//


    assign q = b & d | b & c | a & d | a & c;// Fix me

endmodule

circuit4

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//

assign q = b | c; // Fix me

endmodule

circuit5

module top_module (
    input [3:0] a,
    input [3:0] b,
    input [3:0] c,
    input [3:0] d,
    input [3:0] e,
    output reg [3:0] q );
always @( *) begin
    case (c)
        4'h0:q=b;
        4'h1:q=e;
        4'h2:q=a;
        4'h3:q=d;
        default :
            q = 4'b1111;
    endcase
end
endmodule

circuit6

module top_module (
    input [2:0] a,
    output reg [15:0] q ); 
always @( *) begin
    case (a)
        3'd0:q = 16'h1232;
        3'd1:q = 16'haee0;
        3'd2:q = 16'h27d4;
        3'd3:q = 16'h5a0e;
        3'd4:q = 16'h2066;
        3'd5:q = 16'h64ce;
        3'd6:q = 16'hc526;
        3'd7:q = 16'h2f19;
        default :
            q = 16'h0;

    endcase
end
endmodule

circuit7

module top_module (
    input clk,
    input a,
    output reg q );
always @(posedge clk) begin
    if (a) begin
        q <= 1'b0;
    end
    else
        q <= 1'b1;
end
endmodule

circuit8

module top_module (
    input clock,
    input a,
    output reg p,
    output reg q );
always @( *) begin
    if (clock) begin
        p = a;
    end
end
always @(negedge clock) begin
    q <= p;
//这是一开始的想法    q <= ~q;
end
endmodule

circuit9

module top_module (
    input clk,
    input a,
    output reg [3:0] q );
always @(posedge clk) begin
    if (a) begin
        q <= 4'd4;
    end
    else
        begin
            if (q == 4'd6) begin
                q <= 4'd0;
            end
            else
                q <= q + 1'b1;
        end
end
endmodule

circuit10

module top_module (
    input clk,
    input a,
    input b,
    output q,
    output reg state  );
assign q = (a ^ b) ^ state;
always @(posedge clk) begin
    if (a==0 && b==0) begin
        state <= 1'b0;
    end
    else if (a==1 && b==1) begin
        state <= 1'b1;
    end
    else
        state <= state;
        
end
endmodule