HDLbits Verfication: Writing Testbenches

最新推荐文章于 2023-08-26 00:32:50 发布

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这篇博客展示了几个Verilog模块的实现，包括时钟生成、与门、TFF时钟翻转触发器，以及相应的测试平台。在每个模块中，详细说明了测试平台如何生成输入信号和时钟，并通过示例代码解释了测试激励的设置和时序操作。这些实例对于理解和验证数字逻辑设计非常有帮助。

Verfication: Writing Testbenches

clock

`timescale 1ps / 1ps
module top_module ( );
reg clk;
dut u_dut( .clk(clk) ) ;
initial begin
    clk = 1'b0;
    forever begin
        #(5) clk = ~clk;
    end
end
endmodule

tb1

`timescale 1ps / 1ps
module top_module ( output reg A, output reg B );//

    // generate input patterns here
    initial begin
        A = 1'b0;
        B = 1'b0;
        #10;
        A = 1'b1;
        #5;
        B = 1'b1;
        #5;
        A = 1'b0;
        #20;
        B = 1'b0;
    end

endmodule

and

`timescale 1ps/1ps
module top_module();
reg [1:0] in;
wire out;
andgate u_andgate(
    .in(in),
    .out(out)
);
initial begin
    in = 2'b00;
    #10;
    in[0] = 1'b1;
    #10;
    in[0] = 1'b0;
    in[1] = 1'b1;
    #10;
    in[0] = 1'b1;
end

endmodule

tb2

`timescale 1ps/1ps
module top_module();
reg [2:0] s;
reg clk,in;
wire out;
q7 u_q7(
    .clk(clk),
    .in(in),
    .s(s),
    .out(out)
);
initial begin
    clk = 1'b0;
    forever begin
        #5;
        clk = ~clk;

    end
end
initial begin
    in = 1'b0;
    s = 3'd2;
    #10;
    s = 3'd6;
    #10;
    s = 3'd2;
    in = 1'b1;
    #10;
    s = 3'd7;
    in = 1'b0;
    #10;
    s = 3'd0;
    in = 1'b1;
    #30;
    in = 1'b0;

end
endmodule

tff

`timescale 1ps/1ps
module top_module ();
reg clk,reset,t;
wire q;
tff u_tff(
    .clk(clk),
    .reset(reset),
    .t(t),
    .q(q)
);

initial begin
    clk = 1'b0;
    forever begin       
        #5;
        clk = ~clk;
    end
end
initial begin
    reset = 1'b0;
    t = 1'b0;
    #10;
    reset = 1'b1;
    #10;
    reset = 1'b0;
    t = 1'b1;

end
endmodule
//reset the T flip-flop then toggle it to the "1" state.意思是把t置1