Latex读取代码文件

例子
Verilog代码文件mux.v:

`timescale 1ns / 1ps
module mux_2_to_1(out, i0, i1, sel);
    parameter data_size = 32;

    output [data_size-1:0] out;
    input [data_size-1:0] i0, i1;
    input sel;
    reg [data_size-1:0] out;

    always @(i0, i1, sel) begin
        case (sel)
            1'b0: out = i0;
            1'b1: out = i1;
            default: out = 0;
        endcase
    end
endmodule

Latex程序:

\usepackage{listings}
\lstinputlisting[language=Verilog]{mux.v}

效果：