UVM RAL中前门write与read返回值的理解

write与read的实现具体参见uvm源码中uvm_reg_map.svh，下文代码均来自该文件。

write的发送与返回：

      rw_access.kind    = rw.kind;
      rw_access.addr    = addrs[i];
      rw_access.data    = data;
      rw_access.n_bits  = (n_bits > bus_width*8) ? bus_width*8 : n_bits;
      rw_access.byte_en = byte_en;

      adapter.m_set_item(rw);
      bus_req = adapter.reg2bus(rw_access);
      adapter.m_set_item(null);
      
      if (bus_req == null)
        `uvm_fatal("RegMem",{"adapter [",adapter.get_name(),"] didnt return a bus transaction"});
      
      bus_req.set_sequencer(sequencer);
      rw.parent.start_item(bus_req,rw.prior);

      if (rw.parent != null && i == 0)
        rw.parent.mid_do(rw);

      rw.parent.finish_item(bus_req);
      bus_req.end_event.wait_on();

该部分为do_bus_write任务的内容。首先将读写类型、地址、数据等类型从rw加载到rw_access，通过adapter的reg2bus转换成transaction并发送。

      if (adapter.provides_responses) begin