VHDL 入门 01编程步骤_vhdl map-优快云博客

本文链接：https://blog.youkuaiyun.com/GreatSimulation/article/details/108818639

本文通过一个具体的比较器设计实例，介绍了VHDL语言的基本结构化编程思想。包括顶层设计的端口定义、器件级组件声明、内部信号声明以及实例化端口映射等关键步骤。

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VHDL 语言入门

结构化编程思想 Structural Modeling

本篇以一个比较器例，展示VHDL代码的架构，书写。

Step0 代码总览

entity my_compare is 
port(  A_IN : in std_logic_vector(2 downto 0) ;
       B_IN : in std_logic_vector(2 downto 0) ;
       EQ_OUT : out std_logic);
end my_compare;  

architecture structural of my_compare is  
------------------- component declarations  --------------------
    component big_xnor is  
    port ( A,B: in std_logic;
        F:   out std_logic);
    end component;

    component big_and3 is  
    port (A,B,C: in std_logic;
        F    : out std_logic);
    end component;
-----------------Internal signal declarations ----------------- 
    signal p1_out, p2_out, p3_out: std_logic;
begin
----------------Create instances of components and map ----------
 	x1: big_xnor port map(A=> A_IN(2), B=> B_IN(2), F => p1_out);
    x2: big_xnor port map(A=> A_IN(1), B=> B_IN(1), F => p2_out);
    x3: big_xnor port map(A=> A_IN(0), B=> B_IN(0), F => p3_out);
    a1: big_and3 port map(A=> p1_out, B =>p2_out, C=>p3_out, F=> EQ_OUT)
end structural;

Step1 顶层设计 Generate top-level entity declaration

设计输入输出端口

entity my_compare is 
port(  A_IN : in std_logic_vector(2 downto 0) ;
       B_IN : in std_logic_vector(2 downto 0) ;
       EQ_OUT : out std_logic);
end my_compare;

step2 器件声明 Declare the lower-level design units used

Prepare the component declarations by replacing entity with component
以前写的同或门等是采用顶层设计entity 来写的，现在要将其作为一个component在比较器这个entity来使用，需要进行声明。

component big_xnor is  
port ( A,B: in std_logic;
       F:   out std_logic);
end component;

component big_and3 is  
port (A,B,C: in std_logic;
      F    : out std_logic);
end component;

Step3 内部变量声明 Declare internal signals

除了总输入输出，每个模块中间会有一些临时数据输入输出。
这需要定义内部变量来存放。
注意它放在component后，在begin 前。

architecture structural of my_compare is  
-- component declarations  
    component big_xnor is  
    port ( A,B: in std_logic;
        F:   out std_logic);
    end component;

    component big_and3 is  
    port (A,B,C: in std_logic;
        F    : out std_logic);
    end component;
------- internal signal declarations--------------------------  
    signal p1_out, p2_out, p3_out: std_logic;
begin
  -- ......
end structural;

Step4 构建器件实例Create instances of components and map

构建实例端口对应，需将General A,B,F换成=>实际的输入输出。

begin  
    x1: big_xnor port map(A=> A_IN(2), B=> B_IN(2), F => p1_out);
    x2: big_xnor port map(A=> A_IN(1), B=> B_IN(1), F => p2_out);
    x3: big_xnor port map(A=> A_IN(0), B=> B_IN(0), F => p3_out);
    a1: big_and3 port map(A=> p1_out, B =>p2_out, C=>p3_out, F=> EQ_OUT)